01操作系统精髓与设计原理英汉对照6th.ppt

1、Chapter 1Computer System Overview,Dave Bremer Otago Polytechnic, N.Z.2008, Prentice Hall,Operating Systems:Internals and Design Principles, 6/EWilliam Stallings,Roadmap路标,Basic Elements基本构成 Processor Registers处理器寄存器 Instruction Execution指令的执行 Interrupts中断 The Memory Hierarchy存储器的层次 Cache Memory高速缓存

2、I/O Communication TechniquesI/O通讯技术,Operating System操作系统,Exploits the hardware resources of one or more processors利用硬件资源的一个或多个处理器 Provides a set of services to system users为用户提供一组服务 Manages secondary memory and I/O devices管理辅助存储器和I/O设备,A Computers Basic Elements电脑的基本构成,Processor处理器 Main Memory内存 I/O

3、 Modules输入输出模块 System Bus系统总线,Processor处理器,Controls operation, performs data processing控制操作，执行数据处理 Two internal registers两个内部寄存器 Memory address resister (MAR)地址寄存器 Memory buffer register (MBR)缓冲寄存器 I/O address registerI/O地址寄存器 I/O buffer registerI/O缓冲寄存器,Main Memory内存,Volatile易失的 Data is typically l

4、ost when power is removed Referred to as real memory or primary memory被称作实存储器或主存储器 Consists of a set of locations defined by sequentially numbers addresses由一组单元组成，这些单元由顺序编号的地址定义 Containing either data or instructions存放数据或指令,I/O ModulesI/O模块,Moves data between the computer and the external environmen

5、t such as: Storage (e.g. hard drive)存储器（例如硬盘） Communications equipment通信设备 Terminals终端 Specified by an I/O Address Register由I/O地址寄存器确定 (I/OAR)（I/O地址寄存器）,System Bus,Communication among processors, main memory, and I/O modules在处理器内存和I/O模块间通讯,Top-Level View顶层视图（P7）,Roadmap,Basic Elements Processor Regi

6、sters Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Processor Registers,Faster and smaller than main memory比内存快、小 User-visible registers用户可见寄存器 Enable programmer to minimize main memory references by optimizing register use通过优先使用寄存器减少内存访问 Control and

7、 status registers控制和状态寄存器 Used by processor to control operating of the processor用以控制处理器的操作 Used by privileged OS routines to control the execution of programs由特权操作系统例程使用以控制程序执行,User-Visible Registers用户可见寄存器,May be referenced by machine language可以通过机器语言引用 Available to all programs application progra

8、ms and system programs对所有程序可用（包括应用程序和系统程序） Types of registers typically available are:通常可用的寄存器类型有： data, address, condition code registers.条件码寄存器,Data and Address Registers数据和地址寄存器,Data Often general purpose常常通用 But some restrictions may apply有时会有限制 Address Index Register变址寄存器 Segment pointer堆指针 Sta

9、ck pointer栈指针,Control and Status Registers控制和状态寄存器,Program counter (PC)程序计数器 Contains the address of an instruction to be fetched包含将取指令的地址 Instruction register (IR)指令寄存器 Contains the instruction most recently fetched包含最近取用的指令 Program status word (PSW)程序状态字 Contains status information包含状态信息,Condition

10、 codes条件码,Usually part of the control register通常控制寄存器的一部分 Also called flags也称为标记 Bits set by processor hardware as a result of operations处理器硬件为操作结果设置的位 Read only, intended for feedback regarding the results of instruction execution.只读，用于反馈指令执行结果,Roadmap,Basic Elements Processor Registers Instruction

11、 Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Instruction Execution指令的执行,A program consists of a set of instructions stored in memory处理器执行的程序由一组存储在内存中的指令组成 Two steps两个步骤 Processor reads (fetches) instructions from memory处理器从内存中读取指令 Processor executes each instr

12、uction处理器执行每一条指令,Basic Instruction Cycle基本指令周期,Instruction Fetch and Execute取指令和执行指令,The processor fetches the instruction from memory处理器从内存中读取指令 Program counter (PC) holds address of the instruction to be fetched next程序计数器保存下一条将取指令的地址 PC is incremented after each fetch每次取指令后程序计数器自增,Instruction Regi

13、ster指令寄存器,Fetched instruction is loaded into instruction register取到的指令载入到指令寄存器 Categories操作分类 Processor-memory, 处理器-存储器 processor-I/O, 处理器-I/O Data processing, 数据处理 Control控制,Characteristics of a Hypothetical Machine理想机器的特征,Example of Program Execution程序执行的例子,Roadmap,Basic Elements Processor Registe

14、rs Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Interrupts中断,Interrupt the normal sequencing of the processor中断处理器正常序列 Provided to improve processor utilization用于提高处理器效率 Most I/O devices are slower than the processor Processor must pause to wait for

15、 device,Common Classes of Interrupts中断的通常等级,Flow of Control without Interrupts无中断控制流程,Interrupts and theInstruction Cycle终端和指令周期,Transfer of Control via Interrupts通过中断的控制转移,Instruction Cycle with Interrupts有中断的指令周期,Short I/O Wait短I/O等待,Long I/O wait长I/O等待,Simple Interrupt Processing简单的中断处理,Changes i

16、n Memory and Registers for an Interrupt内存和寄存器因中断而产生的变化,Multiple Interrupts多中断,Suppose an interrupt occurs while another interrupt is being processed.假设当一个中断正在处理，另一个中断出现 E.g. printing data being received via communications line. Two approaches:两个方法 Disable interrupts during interrupt processing在一个中断处

17、理中禁止其他中断 Use a priority scheme.使用优先级,Sequential Interrupt Processing顺序中断处理,Nested Interrupt Processing嵌套中断处理,Example of Nested Interrupts嵌套中断的例子,Multiprogramming多道程序设计,Processor has more than one program to execute处理器有多个程序要执行 The sequence the programs are executed depend on their relative priority a

18、nd whether they are waiting for I/O程序的执行顺序取决于他们的相对优先级以及是否正在等待I/O After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt一个中断处理完成后，控制权可能不会立刻返回到中断时执行到的程序（而可能转移到其他待运行的具有更高优先级的其他程序）,Roadmap,Basic Elements Processor Registers Instruction

19、 Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Memory Hierarchy存储器层次,Major constraints in memory存储器的主要局限 Amount容量 Speed速度 Expense费用 Faster access time, greater cost per bit存取时间越短，每位价格越高 Greater capacity, smaller cost per bit容量越大，每位价格越低 Greater capacity, slower a

20、ccess speed容量越大，存取速度越小,The Memory Hierarchy,Going down the hierarchy沿着结构向下 Decreasing cost per bit每位价格递减 Increasing capacity容量递增 Increasing access time存取时间递增 Decreasing frequency of access to the memory by the processor存储器访问频度递减,Secondary Memory二级存储器,Auxiliary memory（亦）辅助存储器 External外部的 Nonvolatile非

21、易失的 Used to store program and data files用于存储程序和数据文件,Roadmap,Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Cache Memory高速缓存,Invisible to the OS对于操作系统不可见 Interacts with other memory management hardware与其他存储器管理硬件互动 Pro

22、cessor must access memory at least once per instruction cycle每个指令周期处理器至少访问一次内存 Processor speed faster than memory access speed处理器速度远快于内存访问速度 Exploit the principle of locality with a small fast memory利用局部性原理（在处理器和内存间）提供一个容量小速度快的存储器,Principal of Locality局部性原理,More details later but in short 之后更多细节但简而言

23、之 Data which is required soon is often close to the current data最近调用的数据常常和当前数据比较近 If data is referenced, then its neighbour might be needed soon.如果数据被调用了，那么他的邻居可能很快就会被需要了,Cache and Main Memory高速缓存和主存,Cache Principles,Contains copy of a portion of main memory包含部分主存数据的副本 Processor first checks cache处理

24、器首先检查高速缓存 If not found, block of memory read into cache如果没有找到，（有固定字节数的）一块内存读取到缓存 Because of locality of reference, likely future memory references are in that block由于局部性访问，紧接着的内存访问很可能都在这个内存块中,Cache/Main-Memory Structure高速缓存/内存结构,Cache Read Operation高速缓存读操作,Cache Design Issues高速缓存设计问题,Main categories

25、 are:主要分类有 Cache size高速缓存大小 Block size块大小 Mapping function映射函数 Replacement algorithm替换算法 Write policy写策略,Size issues尺寸问题,Cache size高速缓存大小 Small caches have significant impact on performance（适当）小的高速缓存对性能有显著影响 Block size块大小 The unit of data exchanged between cache and main memory（即）高速缓存和主存间数据交换的单位 Lar

26、ger block size means more hits块越大，命中率越高 But too large reduces chance of reuse.但太大会降低重用率,Mapping function映射函数,Determines which cache location the block will occupy确定这个块将占用高速缓存哪个位置 Two constraints:两个约束条件： When one block read in, another may need replaced当一个块读入（高速缓存）时，另一个将会被替代（出高速缓存） Complexity of mapp

27、ing function increases circuitry costs for searching.映射函数越灵活，搜索（以确定某块是否在高速缓存中）（逻辑）电路越复杂,Replacement Algorithm替换算法,Chooses which block to replace when a new block is to be loaded into the cache.当要把一个新块载入cache时，选择要替换哪个块 Ideally replacing a block that isnt likely to be needed again理想上替换掉一个不会再使用的块 Impos

28、sible to guarantee无法保证 Effective strategy is to replace a block that has been used less than others高效的策略要求替换使用最少的块 Least Recently Used (LRU)最近最少使用,Write policy写策略,Dictates when the memory write operation takes place规定何时发生写操作 Can occur every time the block is updated每当块更新时都有可能发生（写操作） Can occur when t

29、he block is replaced（只有）块替换时有可能发生（写操作） Minimize write operations减少（内存）写操作 Leave main memory in an obsolete state使主存处于一种废弃的状态,Roadmap,Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,I/O TechniquesI/O通信技术,When the proce

30、ssor encounters an instruction relating to I/O,当处理器遇到一个与I/O相关的指令时 it executes that instruction by issuing a command to the appropriate I/O module.通过给适当的I/O模块发出命令来执行这个指令 Three techniques are possible for I/O operations:对I/O操作可能有三种技术： Programmed I/O可编程I/O Interrupt-driven I/O中断驱动I/O Direct memory acce

31、ss (DMA)直接内存存取,Programmed I/O,The I/O module performs the requested action 这个I/O模块执行请求动作 then sets the appropriate bits in the I/O status register进而设置相应位的I/O状态寄存器 but takes no further action to alert the processor.但并不进一步提醒处理器 As there are no interrupts, the processor must determine when the instruction is complete因为没有中断，处理器必须决定指令何时完成,Programmed I/OInstruction Set指令集,Control控制 Used to activate and instruct device用于激活和指示设备 Status状态 Tests status conditions测试（I/O及外围设备）状态条件 Transfer传送 Read/write between process register and device在处理器寄存器和外设间读写数据,Programmed I/O Example,Data read in a word at a