altera原版文章：数字预矫正.ppt

1、Digital Predistortion,天马行空官方博客： ；QQ:1318241189；QQ群：175569632,Agenda,Introduction Algorithm Standard lookup table method Phase related errors Memory effect Implementation Multipliers Memory Cordic Processors,天马行空官方博客： ；QQ:1318241189；QQ群：175569632,Introduction: Purpose,Technology demonstrator Show DPD

2、 can be done efficiently on PLD Provide starting point for design Show efficient implementation of key components Provide FPGA benchmark for customer design,Introduction: Predistortion,Algorithms: Overview,Adaptive Lookup Table (LUT) Lookup table for phase and magnitude correction values Deals with

3、magnitude dependent errors Volterra modelling of PA Direct implementation Indirect LUT implementation,Algorithm: Distance Gradient Method,Assumption: Error only depends on magnitude, arctan(I/Q),LUT(r & ),I & QDemod,address,r(I2 +Q2)1/2, arctan(I/Q),r(I2 +Q2)1/2,delay,delay,Qr*cos(),Ir*sin(),I & Qmo

4、d,PA,I,Q in,I,Q out,(-1),(-1),Algorithm: Distance Gradient Method,MATLAB simulation results using SALEH PA model EVM improved in region of 90%,Dist Gradient LUT Freq Plots,Predistortion improves ACLR by 70dB (considering 700-900 and 1100-1300 as side-band regions for measurements) Simplified simulat

5、ion environment (using SALEH PA model),Algorithm: Phase related error,Adds dimension to lookup table Increases memory, logic same size as before Increases time to converge LUT content, LUT content, Without phase error compensation With phase error compensation,Algorithm: Memory effect,Models effect

6、of short term temperature increase on silicon Three possible approaches Add “delta look-up table” (Intersil solution) Add new dimension to LUT (fully adaptive) Use FIR in magnitude address calculation,Algorithm: Memory effect,PA models: Saleh 1 Memoryless, Errors only dependent on input magnitude Vo

7、lterra based, with or without memory: 2,3 Error depend on input magnitude and phase,1 A. Saleh and J.Salz, Adaptive Linearization of Power Amplifiers in Digital Radio Systems, Bell Syst. Tech. J., Vol.62, No. 4, pp 1019-1033, Apr. 1983 2 L.Ding, G.T.Zhou, D.R.Morgan, Z.Ma, J.S.Kenney, J.Kirn and C.R

8、.Giardina, Memory polynomial predistorter based on the indirect learning architecture, Proc.IEEE Global Telecommunications Conference, Taipei, Taiwan, Nov.2002 3. H. Qian, and G.T. Zhou, A neural network predistorter for nonlinear power amplifiers with memory, Proc. 10th IEEE DSP Workshop (DSP2002),

9、 Pine Mountain, GA, October 2002,Algorithm: Memory effect,Error mechanism: Error depends on temperature Temperature depends on previous magnitudes New PA model: Altera model Error depends on current and previous magnitudes Error independent of input phase Solution FIR filter in address calculation,

10、arctan(I/Q),LUT(I & Q),I & Q Demod,address,r(I2 +Q2)1/2, arctan(I/Q),r(I2 +Q2)1/2,delay,I = r*sin() Q = r*cos(),I & Qmod,PA,I,Q in,I,Q out,(-1),(-1),delay,FIR,Processor + hardware acceleration,Predistortion Reference Design,Sync,NCO,FIR,DSP Block Architecture & Resources,High Performance DSP Operati

11、on 18x18 Functions at 282 MHz Input, Output & Pipelining registers Reduce overall Logic usage Add/Accumulate/Subtract Signed & unsigned operations Dynamically change between Add & Subtract,Support complex multiplications (Ar + jAi) x (Br + jBi) = (Ar Br AiBi) + j(Ai Br + ArBi) 4 Multiplications, 1 A

12、ddition & 1 Subtraction, ,- +, arctan(I/Q),LUT(I & Q),I & Q Demod,address,r(I2 +Q2)1/2, arctan(I/Q),r(I2 +Q2)1/2,delay,I = r*sin() Q = r*cos(),I & Qmod,PA,I,Q in,I,Q out,(-1),(-1),delay,FIR,Processor + hardware acceleration,Predistortion Reference Design,Sync,NCO,FIR,TriMatrix Memory,Todays applicat

13、ions need more high performance memory One size does not fit all Wide choice of modes and widths,M512 Blocks,M4K Blocks,M-RAM,External Memory Devices,DDR SDRAM & SRAM SDR SDRAM QDR & QDRII SRAM ZBT SRAM DDR FCRAM,True Dual Port RAM Embedded Shift Register Mode 512K bits Operates Up to 300Mhz,True Du

14、al Port RAM Embedded Shift Register Mode Operates Up to 312Mhz,Rate Changing Embedded Shift Register Mode Operates Up to 312Mhz, arctan(I/Q),LUT(I & Q),I & Q Demod,address,r(I2 +Q2)1/2, arctan(I/Q),r(I2 +Q2)1/2,delay,I = r*sin() Q = r*cos(),I & Qmod,PA,I,Q in,I,Q out,(-1),(-1),delay,FIR,Processor +

15、hardware acceleration,Predistortion Reference Design,Sync,NCO,FIR,CORDIC,Hardware efficient algorithm for computing functions such as: Trigonometric Hyperbolic Logarithmic Iterative solution that uses only shifts and adding/subtracting High performance as no multiplications and divisions Simple/less

16、 hardware required,Altera CORDIC solution for DPD,CORDIC,X_in,Y_in,Z_in,mode,X_out,Y_out,Z_out,Cartesian to Polar conversion X_in, Y_in = Cartesian values, Z_in=0, mode = 0 X_out = magnitude, Z_out = phase Polar to Cartesian conversion X_in = magnitude, Z_in=phase, Y_in=0, mode = 1 X_out, Y_out = Ca

17、rtesian values Mode selects conversion direction Pipelined enabling new inputs to be applied in every clk cycle After initial latency valid outputs will appear on every clk cycle Timesharing : on each clk cycle the mode of the CORDIC can be changed,CORDIC Architecture,Quadrant detect & IP modify,Add

18、/Sub & Shift,Reg,Quadrant Adjust,Iteration 1,Iteration n,Parallel Architecture enabling high performance CORDIC algorithm can only deal with vector rotations of 90 to +90 degrees Require additional logic (Quadrant blocks) to be able to deal with vectors in any of the four quadrants Parameterisable c

19、ode input vector widths and number of iterations can be changed.,CORDIC Implementation,LEs in Altera PLDs Each LE is suited for implementing the required adders/subtractors. LEs can dynamically change from operating as an adder to subtractor Each LE contains a register Performance, arctan(I/Q),LUT(I

20、 & Q),I & Q Demod,address,r(I2 +Q2)1/2, arctan(I/Q),r(I2 +Q2)1/2,delay,I = r*sin() Q = r*cos(),I & Qmod,PA,I,Q in,I,Q out,(-1),(-1),delay,FIR,Processor + hardware acceleration,Predistortion Reference Design,Sync,NCO,FIR,Implementation: Processor?,Should we use processor? For Flexibility Easy to add

21、custom interpolation or similar Low data rate in feedback path at base band Against Straightforward data path (few “IF” branches) Too slow at IF No clear size advantage Difficult to exploit deeply pipelined CORDIC,Performance (Dhrystone MIPS 2.1),20,50,100,200,0,Soft Core,Hard Core,Soft Core Advanta

22、ges Flexibility Low Cost Portable Design Scalability Obsolescence Proof Fits Broad Range of Altera PLD Families,Hard Core Advantages High Performance 922TDMI Time-to-Market Lots of On-Chip Memory Leverage Large Existing Code Base,Excalibur Embedded Processor Cores,Implementation,Forward path: I,Q mu

23、ltipliers Lookup table: Dual port memory Feedback path Nios with custom instructions CORDIC acceleration Multiply acceleration,Target devices,Stratix - Contains DSP Blocks TriMatrix RAM allows for Large lookup tables (multiple dimensions) Suitable if up/down converters are also integrated Cyclone -

24、Extensive use of CORDIC Lowest cost,Ref Design Resource Utilisation Estimates,5000 LEs (50% of avail in 1S10) 4 DSP blocks (67% of avail in 1S10) 3 M4K RAM blocks (5% of avail in 1S10) 2 M512 RAM blocks (2% of avail in 1S10) Assumes 18bit wide I/Q, 64 deep X 32 bit wide LUT. The ref design only cont

25、ains the adaptive lookup table algorithm.,SOPC 3.0 Builder,Build a Custom Companion Chip for Your Processor-Based System With SOPC Builder Interface to Popular Microprocessors PowerPC TI DSP PCI Custom Peripheral Content Communications IP Signal Processing Algorithms Memory Interfaces Hardware Accel

26、eration Functions Security IP Image Processing Traffic Management / Routing Algorithms,Summary,Reference design based on lookup tables on Stratix 1S10 Works for memoryless PA Compensates for memory effect Assumption: Errors independent of phase Can be tuned and modified Open Source extract key compo

27、nents, leave the rest,Discussion ,Development Tools,Quartus II Robust, stable tool for block-based design Includes everything you need to build SOPC designs Interfaces to all leading 3rd party EDA tools SOPC Builder Configures processors, bus architectures, IP and firmware in one simple environment Interfaces to Nios, XA family & popular Microprocessor families DSP Builder Works with MATLAB/Simulink to provide an FPGA