EDA技术与应用讲义 第3章 原理图输入设计方法 QUARTUS II版本.ppt

1、第3章 原理图输入设计方法Quartus II 版操作 课程讲义,合肥工业大学 彭良清,上一章,下一章,本章内容,何时使用 原理图设计输入 常用文件介绍 设计步骤 元件库 和 Altera 宏的使用 如何将VHDL代码文件生成 图形 符号,何时使用 原理图设计输入 ？,符合 传统的 电路设计 习惯 一般只是在 “top-level”(顶层)文件中使用？,Quartus II常用文件介绍,一般步骤,电路的模块划分 设计输入 器件和引脚指配 编译与排错 功能仿真和时序仿真 编程与配置，设计代码的芯片运行,电路的模块划分,人工 根据电路功能 进行 模块划分 合理的模块划分 关系到 电路的性能 实现的

2、难易程度 根据模块划分和系统功能 确定： PLD芯片型号 模块划分后，就可以进行 具体设计 了,设计输入,一般EDA软件允许3种设计输入： HDL语言 电路图 波形输入,图形设计输入的过程,+,+,图形设计:图元,图形设计:端口,如何编写一个新的图形文件？,FILE-NEW出现以下对话窗，选择如下：,如何调入元件？,Edit-Insert Symbol 出现下面窗口,将 自己编写的 符号调入,从 标准库中 调入,将符号之间连线,调入I/O端口元件符号,2类 标准库,Megafunctions/LPM 宏模块 功能复杂、参数可设置的模块 Primitives 基本图元 简单的、功能固定的逻辑元件

3、，不可调整参数,如何将VHDL设计编程Symbol,VHDL文件编译后，自动生成同名的符号文件 符号文件的扩展名称（*.bsf） 调入过程如下：,何为 ？ 器件和引脚指配,器件指配 为设计输入 选择合适的PLD器件型号 何谓引脚指配 将设计代码（图形）中的端口（PORT） 和 PLD芯片的引脚 （PIN） 对应起来的. 指配文件 MAX+PLUS II： “ *.acf ” Quartus II： “ *.qsf ”,器件和引脚指配的方法,方法有2种 在软件的菜单界面中指配 修改指配文件（是文本文件）,菜单界面中 指 配,修改指配文件,CHIP io_2d_lock BEGIN |iVD :I

4、NPUT_PIN = 7; |iHD :INPUT_PIN = 8; |iDENA :INPUT_PIN = 6; |iCLK :INPUT_PIN = 211; |oCLK :OUTPUT_PIN = 237; |oVD :OUTPUT_PIN = 234; |oHD :OUTPUT_PIN = 233; |oDENA :OUTPUT_PIN = 235; . DEVICE = EPF10K30AQC240-2; END; .,编译与排错,编译过程有2种，作用分别为： 语法编译：只是综合并输出网表 编译设计文件，综合产生门级代码 编译器只运行到综合这步就停止了 编译器只产生估算的延时数值 完

5、全的编译：包括编译，网表输出，综合，配置器件 编译器除了完成以上的步骤，还要将设计配置到ALTERA的器件中去 编译器根据器件特性产生真正的延时时间和给器件的配置文件,功能仿真和时序仿真,仿真的概念： 在设计代码下载到芯片前，在EDA软件中对设计的输出进行波形仿真。 常用的2种仿真模式 功能仿真 对设计的逻辑功能进行仿真 时序仿真 对设计的逻辑功能和信号的时间延时进行仿真。 仿真前还要做的工作 输入信号的建立,Quartus II软件中 关于仿真的原文,2种 仿真文件,矢量波形文件： a Vector Waveform File (.vwf) 文本矢量文件 a text-based Vecto

6、r File (.vec),编程与配置,最后， 如果仿真 也正确 的话， 那我们就可以 将设计代码 配置或者编程 到 芯片 中了 编程的文件类型 对于CPLD或者EPC2，ECS1等配置芯片，编程文件扩展名为：“ *.POF “ 配置的文件类型 对于FPGA芯片，配置文件扩展名为：“ *.SOF “,硬件设计和软件设计的时间协调,软件模块划分，器件的初步信号确定（主要是根据需要的I/O引脚的数量） 软件设计，硬件外围电路设计和器件选择 软件仿真 仿真完成后，器件信号的重新审核，进行硬件电路图设计 综合调试 完成,设计的几个问题,如何组织多个设计文件的系统？，项目的概念。 时钟系统如何设计？ 电

7、路的设计功耗 高速信号的软件和硬件设计,The end.,以下内容为正文的引用，可不阅读。,常用EDA工具软件,EDA软件方面，大体可以分为两类： PLD器件厂商提供的EDA工具。较著名的如： Altera公司的Max+plusII和QuartusII、 Xilinx公司的FoundationSeries、 Latice-Vantis公司的ispEXERTSystem。 第三方专业软件公司提供的EDA工具。常用的有： Synopsys公司的FPGACompilerII、 ExemplarLogic公司的LeonardoSpectrum、 Synplicity公司的Synplify。 第三方工具

8、软件是对CPLD/FPGA生产厂家开发软件的补充和优化，如通常认为Max+plusII和QuartusII对VHDL/VerilogHDL逻辑综合能力不强，如果采用专用的HDL工具进行逻辑综合，会有效地提高综合质量。,ALTERA 公司的EDA合作伙伴,硬件描述语言：起源,是电子电路的文本描述。 最早的发明者：美国国防部，VHDL,1983 大浪淘沙，为大者二： VHDL 和 Verilog HDL 其他的小兄弟： ABEL、AHDL、System Verilog、System C。,一个D触发器的VHDL代码例子,- VHDL code position: p83_ex4_11_DFF1 -

9、 - LIBARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT (CLK:INBIT; D:INBIT; Q:OUTBIT ); END ENTITY DFF1; ARCHITECTURE bhv OF DFF1 IS BEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND (CLK=1) AND ( CLKLAST_VALUE = 0) THEN - 严格的CLK信号上升沿定义 Q = D; END IF; END PROCESS; END ARCHITECTURE bhv;,代码实体（510）,

10、代码结构体（1120）,如何使用VHDL来设计电路？,VHDL设计电路的的5步曲 语言编码 逻辑综合 功能和时序仿真 器件适配 器件编程,使用MAX+PLUS II软件的设计过程,MAX+PLUS II设计过程说明,Compiler Netlist Extractor（编译器网表提取器）: 通过该过程生成设计项目的网表文件, Database Builder(数据库构建器 ): 用于将所有的设计文件集成到项目数据库中 如果指定端口的实体已被抽取. 则从盘中读取. cnf文件信息就可以了, 因而节省了时间. Logic Synthesizer (逻辑综合器): 选择合适的逻辑化简算法, 去除冗余

11、和无用逻辑, 有效使用器件的逻辑资源. Fitter(适配器) 将电路适配到某个PLD器件中。 Timing SNF Extractor(时序SNF文件提取器) 产生用于时序仿真的网表文件 Assembler（汇编器） 产生用于器件编程的目标代码,其他的HDL综合工具,Altera公司 MAX+PLUS II 10.2（已经停止发行，新器件不支持） QUARTUS II 5.0（推荐使用） Xilinx 公司 ISE 7.0：Xilinx公司集成开发的工具 Foundation: Xilinx公司早期开发工具，逐步被ISE取代 ISE Webpack： Webpack是xilinx提供的免费开

12、发软件，功能比ISE少一些，可以从xilinx网站下载,有了HDL语言后？,硬件设计人员 的工作过程 已经 类似与 软件设计人员，那么 这种模式的好处是？ 让我们先看看原来是如何做的,Compiler Netlist Extractor（编译器网表提取器）,The Compiler module that converts each design file in a project (or each cell of an EDIF Input File) into a separate binary CNF. The filename(s) of the CNF(s) are based on

13、 the project name. Example The Compiler Netlist Extractor also creates a single HIF that documents the hierarchical connections between design files. This module contains a built-in EDIF Netlist Reader, Verilog Netlist Reader, VHDL Netlist Reader, and converters that translate ADFs and SMFs for use

14、with MAX+PLUS II. During netlist extraction, this module checks each design file for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together. 返回,Database Builder(数据库构建器 ):,The Compiler module that builds a single, fully flattened project database that in

15、tegrates all the design files in a project hierarchy. The Database Builder uses the HIF to link the CNFs that describe the project. Based on the HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the database as many times as it is used within the ori

16、ginal hierarchical project. The database thus preserves the electrical connectivity of the project. The Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the fully optimized project. In the beginning, the datab

17、ase contains only the original netlists; at the end, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming. As it creates the database, the Database Builder examines the logical completeness and consistency of the project, and chec

18、ks for boundary connectivity and syntactical errors (e.g., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing. 返回,Logic Synthesizer,The Compiler module that synthesizes the logic in a projects design files. Using the data

19、base created by the Database Builder, the Logic Synthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications. For projects that use JK or SR flipflops, the Logic Synthesizer checks each case to determine whether a D or T flipflop wil

20、l implement the project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly. The Logic Synthesizer also synthesizes equations for flipflops to implement state registers of state machines. An equation for each state bit is optima

21、lly implemented with either a D or T flipflop. If no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the state machine. These encodings are chosen to minimize the resour

22、ces used. 返回,Fitter（适配器）,The Compiler module that fits the logic of a project into one or more devices. Using the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the available resources of one or more devices. It assigns each logic function to the b

23、est logic cell location and selects appropriate interconnection paths and pin assignments. The Fitter attempts to match any resource assignments made for the project with the resources on the device. If it cannot find a fit, the Fitter allows you to override some or all of your assignments or termin

24、ate compilation. The Fitter module generates a Fit File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful compilation. Each time the project compiles successfully, the Fit File is overwritten. You can back-annotate the assign

25、ments in the file to preserve them in future compilations. 返回,Timing SNF Extractor(时序SNF文件提取器),The Compiler module that creates a timing SNF containing the logic and timing information required for timing simulation, delay prediction, and timing analysis. The Timing SNF Extractor is turned on with t

26、he Timing SNF Extractor command (Processing menu). It is also turned on automatically when you turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). The Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor or t

27、he Linked SNF Extractor. A timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis

28、 (including delay prediction) are available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional testing is available only for a single-device project. 返回,Assembler（汇编器）,The Compiler module that cr

29、eates one or more programming files for programming or configuring the device(s) for a project. The Assembler module completes project processing by converting the Fitters device, logic cell, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, Hex F

30、iles, TTFs, Jam Files, JBC Files, and/or JEDEC Files. POFs and JEDEC Files are always generated; SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX 8000 or FLEX 10K devices; and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE

31、or MAX 3000A projects. If you turn on the Enable JTAG Support option in the Classic & MAX Global Project Device Options dialog box (Assign menu) or the Classic & MAX Individual Device Options dialog box, the Assembler will also generate Jam Files and JBC Files for MAX 7000A or MAX 7000S projects. Af

32、ter compilation, you can also use SOFs to create different types of files for configuring FLEX 6000, FLEX 8000 and FLEX 10K devices with Convert SRAM Object Files (File menu). The programming files can then be processed by the MAX+PLUS II Programmer and the MPU or APU hardware to produce working dev

33、ices. Several other programming hardware manufacturers also provide programming support for Altera devices. 返回,Simulation Mode,Functional Simulates the behavior of flattened netlists extracted from the design files. You can use Tcl commands and scripts to control simulation and to provide vector sti

34、muli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec), although the Simulator uses only the sequence of logic level changes, and not their timing, from the vector stimuli. This type of simulation also allows you to check simulation coverage (th

35、e ratio of output ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist). Timing Uses a fully compiled netlist that includes estimated or actual timing information. You can use Tcl commands and scripts to control simulation and

36、 to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec). This type of simulation also allows you to check setup and hold times, detect glitches, and check simulation coverage (the ratio of output ports actually toggling betw

37、een 1 and 0 during simulation, compared to the total number of output ports present in the netlist). Timing using Fast Timing Model Performs a timing simulation using the Fast Timing Model to simulate fastest possible timing conditions with the fastest device speed grade,Megafunctions/LPM,Arithmetic

38、 Components Gates I/O Components Memory Compiler Parallel Flash Loader Megafunction SignalTap II Logic Analyzer Megafunction Storage Components,Arithmetic Components,altaccumulate divide* altfp_add_sub lpm_abs altfp_mult lpm_add_sub altmemmult lpm_compare altmult_accum lpm_counter altmult_add lpm_divide altsqrt lpm_mult altsquare parallel_add,Gates,busmuxlpm_inv lpm_andlpm_mux lpm_bustri lpm_or lpm_clshift lpm_xor lpm_constant mux lpm_decode,I/O Components,altcdr_rxaltdqs altcdr_tx altgxb altclkctrl altlvds