英文翻译1：AT89C51应用及其编程方法

1、个人收集整理资料,仅供交流学习,勿作商业用途AT89C51地应用及其编程方法1 AT89C51 应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调 控制系统，汽车发动机和其他一些领域.这些单片机地高速处理速度 和增强型外围设备集合使得它们适合于这种高速事件应用场合.然而,这些关键应用领域也要求这些单片机高度可靠.健壮地测试环境和用 于验证这些无论在元部件层次还是系统级别地单片机地合适地工具 环境保证了高可靠性和低市场风险.Intel 平台工程部门开发了一种 面向对象地用于验证它地AT89C51汽车单片机多线性测试环境.这种 环境地目标不仅是为AT89C51汽车单片机提供一种健壮测试

2、环境，而 且开发一种能够容易扩展并重复用来验证其他几种将来地单片机.开发地这种环境连接了 AT89C51本文讨论了这种测试环境地设计和原 理，它地和各种硬件.软件环境部件地交互性，以及如何使用AT89C51. 1.1介绍8位AT89C51 CHMOS艺单片机被设计用于处理高速计算和快 速输入/输出.MCS51单片机典型地应用是高速事件控制系统.商业应 用包括调制解调器，电动机控制系统，打印机，影印机，空调控制系统， 磁盘驱动器和医疗设备.汽车工业把MCS51单片机用于发动机控制系 统，悬挂系统和反锁制动系统.AT89C51尤其很好适用于得益于它地 处理速度和增强型片上外围功能集，诸如：汽车动力

3、控制，车辆动态悬 挂，反锁制动和稳定性控制应用.由于这些决定性应用，市场需要一种 可靠地具有低干扰潜伏响应地费用-效能控制器，服务大量时间和事个人收集整理资料,仅供交流学习,勿作商业用途件驱动地在实时应用需要地集成外围地能力，具有在单一程序包中高 出平均处理功率地中央处理器.拥有操作不可预测地设备地经济和法 律风险是很高地.一旦进入市场，尤其任务决定性应用诸如自动驾驶 仪或反锁制动系统，错误将是财力上所禁止地.重新设计地费用可以 高达500K美元，如果产品族享有同样内核或外围设计缺陷地话，费用会更高.另外,部件地替代品领域是极其昂贵地，因为设备要用来把模 块典型地焊接成一个总体地价值比各个部件

4、高几倍.为了缓和这些问题,在最坏地环境和电压条件下对这些单片机进行无论在部件级别还 是系统级别上地综合测试是必需地,Intel Chandler 平台工程组提供了各种单片机和处理器地系统验证,这种系统地验证处理可以被分 解为三个主要部分,系统地类型和应用需求决定了能够在设备上执行 地测试类型.AT89C51提供以下标准功能：4k字节FLASH闪速存储器，128字节内部RAM,32个I/O 口线,2 个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通 信口，片内振荡器及时钟电路,同时,AT89C51降至0Hz地静态逻辑操 作，并支持两种可选地节电工作模式,空闲方式体制CPU地工作，但

5、允 许RAM定时/计数器，串行通信口及中断系统继续工作,掉电方式保存 RAM中地内容，但振荡器体制工作并禁止其他所有不见工作直到下一 个硬件复位.个人收集整理资料,仅供交流学习,勿作商业用途图1-2-1 AT89C51方框图引脚功能说明Vcc：电源电压GND 地P0 口: P0 口是一组8位漏极开路型双向I/O 口，也即地址/ 数据总线复用.作为输出口用时，每位能吸收电流地方式驱动8个TTL 逻辑门电路，对端口写“1”可作为高阻抗输入端用.在访问外部数据 存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总 线复用，在访问期间激活内部上拉电阻.在Flash编程时,P0 口接受 指令字节

6、，而在程序校验时,输出指令字节，校验时,要求外接上拉电 阻.P1 口: P1是一个带内部上拉电阻地8位双向I/O 口,P1地输个人收集整理资料,仅供交流学习,勿作商业用途出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路.对端口写“1”，通过内部地上拉电阻把端口拉到高电平，此时可作输入口 .作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低 时会输出一个电流（IIL ） .Flash编程和程序校验期间,P1接受低8 位地址.P2 口： P2是一个带有内部上拉电阻地8位双向I/O 口,P2地 输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路.对端口写“1”，通过内部地上拉电阻

7、把端口拉到高电平，此时可作输入口 .作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉 低时会输出一个电流（IIL ）.在访问外部程序存储器或16位四肢地 外部数据存储器（例如执行MOVDPTR令）时,P2 口送出高8位地 址数据，在访问8位地址地外部数据存储器（例如执行 MOVX RI指 令）时,P2 口线上地内容（也即特殊功能寄存器（SFR区中R2寄存 器地内容），在整个访问期间不改变.Flash编程和程序校验时,P2也 接收高位地址和其他控制信号.P3 口： P3是一个带有内部上拉电阻地8位双向I/O 口,P3地 输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路.对端口写

8、“1”，通过内部地上拉电阻把端口拉到高电平，此时可作输入口 .作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉 低时会输出一个电流（IIL ） .P3 口还接收一些用于Flash闪速存储 器编程和程序校验地控制信号.RST复位输入.当振荡器工作时，RST引脚出现两个机器周期个人收集整理资料,仅供交流学习,勿作商业用途以上高电平将使单片机复位.ALE/PROG当访问外部程序存储器或数据存储器时，ALE （地址 锁存允许）输出脉冲用于锁存地址地低 8位字节.即使不访问外部存 储器,ALE仍以时钟振荡频率地1/6输出固定地正脉冲信号，因此它 可对外输出时钟或用于定时目地.要注意地是，每当

9、访问外部数据存 储器时将跳过一个ALE脉冲.对Flash存储器编程期间，该引脚还用 于输入编程脉冲（PROG.如有必要，可通过对特殊功能寄存器（SFR 区中地8EH单元D0位置位，可禁止ALE操作.该位置位后，只有一条 MOV*口 MOVG旨令ALE才会被激活.此外，该引脚会被微弱拉高，单片 机执行外部程序时，应设置ALE无效.PSEN程序存储允许输出是外部程序存储器地读选通型号 ，当 89C51由外部存储器取指令（或数据）时，每个机器周期两次PSEN有 效，即输出两个脉冲.在此期间，当访问外部数据存储器，这两次有效 地PSEN信号不出现.EA/VPP外部访问允许.欲使CPU仅访问外部程序存储

10、器（地 址为0000H-FFFFH ,EA端必须保持低电平（接地）.需注意地是： 如果加密位LB1被编程，复位时内部会锁存EA端状态.如EA端为高 电平（接Vcc端），CPU则执行内部程序存储器中地指令.Flash存储 器编程时，该引脚加上+12v地编程允许电源Vpp,当然这必须是该器 件使用12v编程电压Vpp.XTAL1振荡器反相放大器及内部时钟发生器地输入端.个人收集整理资料,仅供交流学习,勿作商业用途 XTAL2振荡器反相放大器地输出端.89C51中有一个用于构成 内部振荡器地高增益反相放大器，引脚XTAL1和XTAL盼别是该放大 器地输入端和输出端.这个放大器与作为反馈元件地片外石英

11、晶体或 陶瓷谐振器一起构成自激振荡器，振荡电路参见图5.外接石英晶体或 陶瓷谐振器及电容C1.C2接在放大器地反馈回路中构成并联振荡电 路.对电容C1,C2虽没有十分严格地要求，但电容容量地大小会轻微 影响振荡频率地高低.振荡器工作地稳定性.起振地难易程度及温度 稳定性，如果使用石英晶体，我们推荐电容使用30Pf10 Pf,而如使 用陶瓷谐振器建议选择40Pf 土 10Pf,用户也可以采用外部时钟.这种 情况下，外部时钟脉冲接到 XTAL1端，即内部时钟发生器地输入端 XTAL2则悬空.,掉电模式：在掉电模式下，振荡器停止工作，进入掉电模式地指令是最后一 条被执行地指令，片内RAM和特殊功能寄

12、存器地内容在终止掉电模式 前被冻结.推出掉电模式地唯一方法是硬件复位，复位后将重新定义 全部特殊功能寄存器但不改变 RAM中地内容，在Vcc恢复到正常工作 电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定 工作.89C51地程序存储器阵列是采用字节写入方式编程地，每次写 入一个字符，要对整个芯片地EPRO唬序存储器写入一个非空字节， 必须使用片擦除地方法将整个存储器地内容清楚.2编程方法编程前，设置好地址.数据及控制信号，编程单元地地址加在 P1个人收集整理资料,仅供交流学习,勿作商业用途口和P2 口地P2.0 P2.3 （11位地址范围为0000H-0FFFH，数据从P0口输入，

13、弓I脚P2.6.P2.7 和P3.6.P3.7 地电平设置见表 6,PSEB 为低电平,RST保持高电平，EA/Vpp引脚是编程电源地输入端，按要求 加上编程电压，ALE/PROGI脚输入编程脉冲（负脉冲）.编程时,可采 用420MHz地时钟振荡器，89C51编程方法如下：在地址线上加上要 编程单元地地址信号在数据线上加上要写入地数据字节.激活相应地控制信号.在高电压编程方式时,将EA/Vpp端加上+12v编程电压.每 对Flash存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE/PRO颂程月冲.改变编程单元地地址和写入地数据，重复15步骤，知道全部文件编程结束.每个字节写入周期是自

14、身定时地，通常 约为1.5ms. 数据查询89C51单片机用数据查询方式来检测一个写 周期是否结束，在一个写周期中，如需要读取最后写入地那个字节，则 读出地数据地最高位（P0.7）是原来写入字节地最高位地反码.写周 期开始后，可在任意时刻进行数据查询.Ready/Busy:字节编程地进度可通过Ready/Busy输出信号检测，编程期 间,ALE变为高电平 H后P3.4 （Ready/Busy）端被拉低，表示正在 编程状态（忙状态）.编程完成后,P3.4变为高电平表示准备就绪状 态.程序校验：如果加密位LB.LB2没有进行编程，则代码数据可通 过地址和数据线读回原编写地数据，采用下图地电路，程序

15、存储器地 地址由P1 口和P2 口地P2.0 P2.3输入，数据由P0 口读个人收集整理资料，仅供交流学习，勿作商业用途出，P206.P2.7 和P3.6.P3.7 地控制信号见表6,PSEN保持低电平,ALE.EA和RST保持高电平.校验时,P0 口必须接上10k左右地上拉电阻.ADOOOOH/OFI FHSEE FLASHiPROiGiRAMMlNG MODES TABLEa-24 MHZP1F2 O -F2.3 ROP2 GP2 .7ALEP3 6P3.7XTAJ-ZEAXTAL1IRSTONOPSENA7Al 1DATA图2-1-1编程电路ADDR.OOOOH/OFFTHA8A11A7

16、POPGM DATA (USE 10K PULLUPS)SEE FLASHPROGRAMMI NGMODES TABLE3-24 MHzP2 7X1AL2X1AL1GNDALEEARSTPSEN图2-2-2 校验电路2.2芯片擦除：利用控制信号地正确组合（表6）并保持ALE/PROCSI脚10ms地低 电平脉冲宽度即可将EPROM车列（4k字节）和三个加密位整片擦除， 代码阵列在片擦除操作中将任何非空单元写入“1，这步骤需在编程之前进行.个人收集整理资料,仅供交流学习,勿作商业用途读片内签名字节：89C51单片机内有3个签名字节，地址为030H.031H和032H.于 声明该器件地厂商.号和编

17、程电压.读签名字节地过程和单元 030H.031H和032H正常校验相仿，只需要将P3.6和P3.7保持低电 平,返回值意义如下：(030H) = 1EH 声明产品由ATMEL公司制造.(031H) = 51H 声明为89C51单片机.(032H) = FFH 声明为12V编程电压.(032H) = 05H 声明为5编程电压.编程接口：采用控制信号地正确组合可对 Flash闪速存储阵列中地每一代 码字节进行写入和存储器地整片擦除，写操作周期是自身定时地，初 始化后它将自动定时到操作完成.微机接口实现两种信息形式地交换 在计算机之外，由电子系统所处理地信息以一种物理信号形式存在，但在程序中，它是

18、用数字表示地.任一接口地功能都可分为以某种形 式进行数据库变换地一些操作，所以外部和内部形式地转换是由许多 步骤完成地.模拟-数字转换器(ADC用来将连续变化信号变成相应 地数字量，这数字量可是可能性地二进制数值中地一固定值.如果传感器输出不是连续变化地，就不需模拟-数字转换.这种情况下，信号 调理单元必须将输入信号变换成为另一信号，也可直接与接口地下一部分，即微计算机本身地输入输出单元相连接.输出接口采用相似地形式，明显地差别在于信息流地方向相反；是从程序到外部世界.这种个人收集整理资料,仅供交流学习,勿作商业用途情况下，程序可称为输出程序，它监督接口地操作并完成数字-模拟转 换器（DAC所

19、需数字地标定.该子程序依次送出信息给输出器件，产 生相应地电信号，由DAC转换成模拟形式.最后，信号经调理（通常是 放大）以形成适应于执行器操作地形式.在微机电路中使用地信号几 乎总是太小而不能被直接地连到“外部世界”，因而必须用某种形式将其转换成更适宜地形式.接口电路部分地设计是使用微机地工程师 所面临最重要地任务之一.我们已经了解到微机中，信号以离散地位 形式表示.当微机要与只有打开或关闭操作地设备相连时,这种数字形式是最有用地，这里每一位都可表示一开关或执行器地状态.为了解决实际问题，一个单片机不仅包括CPU程序和数据存储器，另外，它 必须含有通过CPU访问外部信息地硬件.一旦CPU收集

20、到数据信息和 流程，它必须能够改变外部领域地一部分，这些硬件设备称作外围设 备，它们是CPU通往外部地窗口 .单片机可利用外围设备中最基本地用于一般用途地I/O接口，每个I/O接口既可作为输入端又可作为输出端，每个I/O接口地功能取 决与程序初始化阶段对数据方位寄存器相应位进行置一和清零操作，通过CPU指令对数据寄存器相应位进行置一和清零来置一和清零输 出端口，同样输入端口逻辑位也可以通过 CPU指令访问.一些类型地 串行口单元允许CPU与外部设备进行串口通信，用串口位代替平行位 进行通信需要少许地I/O 口，这样使通信费用降低但速度也相对慢些 串口传送可以同步也可以异步.个人收集整理资料,仅

21、供交流学习,勿作商业用途The application and programming algorithm of AT89C511 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and en

22、hanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing proc

23、ess and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of itsAT89C51 automotive microcontrollers. The goals of

24、 this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction个人收集整理资料,

25、仅供交流学习,勿作商业用途with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handl

26、e high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. Th

27、e automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive

28、power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, abilityto service the high numberof time and event driven int

29、egratedperipherals needed in real个人收集整理资料,仅供交流学习,勿作商业用途time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such

30、as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components

31、is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system levelunder worst case environ

32、mental andvoltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of vario

33、us micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types个人收集整理资料,仅供交流学习,勿作商业用途of testing are performed on the device.The AT89C51 provides the following standard features:4Kby

34、tes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two softw

35、are selectable power saving modes. The Idle Modestops the CPUwhile allowing the RAM,timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAMcontents but freezes the oscillator disabling allother chip functions until the next hardware reset.-料-J-11

36、 口MT a EUHJWHH | mHT 3! lOmrUVHB：TRI0一上昌Figure 1-2-1Block DiagramAkin TiU H K. OTZKH.中 IWLRJ TPin DescriptionVCC Supply voltage.个人收集整理资料,仅供交流学习,勿作商业用途GND Ground.Port 0 : Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When1s are written t

37、o port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured tobe themultiplexed low order address/data bus during accesses to external program and data memory. In this modeP0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outpu

38、ts the code bytes during program verification. External pullups are required during program verification.Port 1 : Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by th

39、e internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2 : Port 2 is an 8-bit bi-directional I

40、/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are个人收集整理资料,仅供交流学习,勿作商业用途pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I

41、IL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during

42、 fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR)n this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2

43、 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3 : Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written t

44、o Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special feature个人收集整理资料,仅供交流学习,勿作商业用途soft the AT89C51 as list

45、ed below:RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash p

46、rogramming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bi

47、t 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVXor MOVCinstruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEIN Program Store Enable is the read strobe to external program me

48、mory. WhentheAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSENactivations are skipped during each access to external data memory.EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch cod

49、e from external个人收集整理资料,仅供交流学习,勿作商业用途program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EAwill be internally latched on reset. EA should be strapped to VCC for internalprogram executions. This pin all receives the 12-volt programming enable volta

50、ge (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1： Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respecti

51、vely, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shownin Figure 1. Either a quarts crystal or ceramic resonator may be used.To drive the device from an external clock source, XTAL2should be left unconnected while XTAL1 is driven as shown in Figure2.There a

52、re no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimumand maximum voltage high and low time specificationsmust beobserved. Idle ModeIn idle mode, the CPUputs itselfto sleepwhile all the o

53、n chip peripherals remain active. The mode isinvoked by software. The content of the on-chip RAMand all the个人收集整理资料,仅供交流学习,勿作商业用途special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that whe

54、n idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAMin this event, but access to the port pins is not inhibited. T

55、o eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instructi

56、on that invokes power-down is the last instruction executed. The on-chip RAMand Special Function Registers retain their values until the power-down modeis terminated. The only exit from power-down is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not

57、be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory个人收集整理资料,仅供交流学习,勿作商业用途array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chi

58、p Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following

59、 steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPPto 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or t

60、he lock bits.The byte-write cycle isself-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51features Data Polling to indicate the end of a write cycle. Du