A 13.56Mbps PSK Receiver for 13.56MHz RFID Applications.pdf

1、A 13.56Mbps PSK Receiver for 13.56MHz RFID Applications R.C.H. van de Beek1, M. Ciacci1, G. Al-Kadi1, P. Kompan2, M. Stark2 1 NXP Semiconductors, Eindhoven, the Netherlands, 2 NXP Semiconductors, Gratkorn, Austria Abstract This paper presents a receive chain for very- high bit rate (VHBR) communicat

2、ion over a short range 13.56MHz inductively coupled interface, using multi-bit-per- symbol phase-shift keying (PSK) as proposed for the ISO14443 VHBR amendment. A data rate of up to 13.56Mbps is achieved. The receiver consists of an analog front-end IC followed by an FPGA-based digital baseband proc

3、essor (DSP). The analog front-end IC recovers the carrier from the antenna signal and performs PSK demodulation using an 8-bit time-to-digital converter (TDC). It consumes 100A in the 13.56Mbps data rate mode. The FPGA-based DSPs main functions are symbol clock recovery in a closed-loop with the ana

4、log front-end as well as adaptive equalization. Target bit error rates of below 210-4 were achieved for transmitted field strengths above 1.2A/m. Index Terms Wireless communication, Phase Shift Keying, Phase Locked Loops, Time-to-digital conversion, CMOS. I. INTRODUCTION Recent interest in increasin

5、g the maximum data rate of 13.56MHz inductively coupled communication links according to ISO/IEC 14443 have spawned standardization amendment proposals 1. For communication rates higher than 6.78Mbps from Proximity Coupling Device (PCD) to Proximity Integrated Circuit Card (PICC), a multi-bit incomp

6、lete-circle phase- shift keying (PSK) has been proposed. In such modulation, up to four bits are coded in each transmitted PSK symbol. This paper presents a PICC PSK receive chain capable of receiving bit rates up to and including 13.56Mbps, which is 16 times the current maximum ISO/IEC 14443 data r

7、ate of 848kbps. The communication from PICC to PCD is outside the scope of this paper. Section II introduces the relevant details of the Physical Layer in the communication direction from PCD to PICC for bit rates higher than 6.78Mbps and the architecture of the presented receiver. Section III then

8、focuses on the implementation of the analog front-end (AFE) of the PSK receiver, which delivers digitized information to the FPGA-based digital signal processor (DSP). The DSP is described in section IV. Section V discusses some measured results, both of the stand-alone AFE as well as the complete r

9、eceiver. The paper concludes in section VI, where the results that were achieved are summarized. II. PHYSICAL LAYER The PCD transmits data to the PICC by modulating the magnetic field that it emits. In order to support bit rates above 6.78Mbps, a multi-bit-per-symbol PSK modulation is used. Various

10、combinations of the symbol rate fsym and PSK order are possible, yielding the raw data rates as specified in Table I, where fc equals the carrier frequency of 13.56MHz. This work focused on realizing data rates up to 13.56Mbps, using symbol rates of fc/4. Fig. 1. PSK constellation diagram using circ

11、le segment. Fig. 2. Data flow through inductively coupled channel for communication from PCD to PICC. The PSK modulation uses a circle segment rather than a full circle, as illustrated by the constellation diagram in Fig. 1. In the case of 8-PSK the points are separated by 8, in the case of 16-PSK t

12、here are 4 between the points. There are three main advantages of using a circle segment rather than a full circle for the PSK modulation. Firstly, using a circle segment ensures that no symbol transition exists that would result in passing close to the constellation origin, thus resulting in low am

13、plitude glitches. This is beneficial in delivering a constant power to the (passive) PICC, obviating its need for large and expensive supply decoupling capacitors. Secondly, employing a circle segment introduces significant carrier energy, whereas full-circle PSK is a suppressed-carrier modulation.

14、This allows for higher TABLE I PSK data rates in Mbps PSK order fsym 8 16 fc/4 10.17 13.56 fc/2 20.34 27.12 239 RMO4A-1 978-1-4673-0416-0/12/$31.00 2012 IEEE2012 IEEE Radio Frequency Integrated Circuits Symposium PCD field strengths before violating the spectral regulations for 13.56MHz proximity co

15、upled systems, which are clearly designed to allow for energy transfer mostly in the carrier, e.g. 2. Thirdly, the introduced carrier allows for simple carrier recovery techniques to be employed in the typically crystal-less PICC. A standard integer-N phase-locked loop (PLL) can be used rather than

16、a much more complex Costas loop, the latter typically used for full-circle PSK carrier recovery. The data flow through the physical layer from (channel coded) source data on the transmitting PCD side to the data replica on the receiving PICC end is shown in Fig. 2. First, Gray mapping is applied to

17、the source data stream, thus minimizing the bit error rate given a certain symbol error rate. Then the data is differentially encoded, such that the information is encoded in phase changes of the carrier rather than in the absolute phase. One advantage of using differential coding is that the invers

18、e operation (the differential decoder) de-emphasizes low-frequency phase noise, see section V. After PSK modulation the signal passes the inductively coupled antennas. On the PICC side, applying the inverse operations then yields the data replica. Note that each transmitted frame is preceded by a pr

19、e- defined start-of-communication (SOC) sequence, that can be used for example for channel estimation and symbol clock recovery. C. PICC system build-up The PICC PSK receive chain is illustrated in Fig. 3. Fig. 3. The complete PSK receiver architecture. Connected to the credit-card sized inductive l

20、oop antenna is the AFE IC, implemented in a 140nm CMOS process, which is subject of the next section. The AFE converts the phase information present in the received signal into the digital domain. The information is then further processed by the digital signal processor (DSP), implemented on an FPGA

21、 here, which, amongst others, equalizes the signal in order to cope with inter-symbol interference (ISI). The recovered information is captured and analyzed by a host PC. III. ANALOG PICC FRONT-END As illustrated in Fig. 3, the AFE has three main functions. Firstly, it contains a voltage rectifier a

22、nd limiter for supply generation. Unfortunately, this network forms a non-linear load to the antenna, strongly compressing amplitude variations across the antenna. Fig. 4. Dual charge pump carrier recovery PLL. Secondly, since typical PICCs do not have a local frequency reference, there is a carrier

23、 recovery PLL that extracts the carrier from the PSK-modulated antenna signal. Finally, the conversion of the phase information to the digital domain is done by a Time-to-Digital converter (TDC). The carrier-recovery PLL, see Fig. 4, is built around a current-controlled ring oscillator (CCO), operat

24、ing at 108.48MHz, thus reducing the circuit implementation area as compared to operating at the carrier frequency directly. A fixed divide-by-eight frequency divider outputs the recovered 13.56MHz carrier and closes the loop. Phase detection is done using a standard three-state phase frequency detec

25、tor (PFD) whose output signals control two charge pumps (CPs). The integral CP delivers its charge to a purely capacitive loop filter. A PMOS- based transconductor stage then converts the voltage across this capacitor to a CCO control current. Loop damping is achieved by the proportional CP, that de

26、livers its current to the CCO via a first order RC low pass filter, bypassing the transconductor stage. This bypass makes the loop bandwidth virtually independent of the transconductance gm and, with that, much less sensitive to process, voltage and temperature variations than with a single-CP PLL 3

27、. Such low bandwidth sensitivity is desirable since the carrier recovery PLL is part of the signal path and its transfer needs to be compensated for in the DSP. The PSK demodulation is done by the TDC, which measures the time difference between zero-crossings in the PSK modulated signal coming from

28、the antenna buffer and those in the recovered carrier. This measured quantity is then converted to the digital domain for further processing in the DSP. 240 Fig. 5. Time-to-digital converter. Fig. 6. Chip Photograph of the analog front-end IC. The inset shows the Cadence layout view of the PSK demod

29、ulator core. The TDC, illustrated in Fig. 5, performs this conversion in two steps: a time-to-voltage conversion followed by an analog-to-digital conversion step (ADC), similar to 4. The ADC is an 8-bit successive-approximation register (SAR) ADC that uses a capacitive charge redistribution digital-

30、to-analog converter (DAC) in its feedback path 5. This DAC capacitor array also functions as the integration capacitor in the time-to-voltage conversion process, such that track-and-hold circuitry is not needed in this architecture, unlike the TDC of 4. The TDC performs an integrate-and-dump functio

31、n based on the control signal marked Integrate in Fig. 5: during the high-phase of this control signal, the phase detector and CP combination perform the time-to-voltage conversion, after which the differential voltage across the DAC capacitor array is proportional to the time shift between the modu

32、lated antenna input and the recovered carrier. The SAR algorithm converts this voltage to the digital domain after the high-to-low transition of the Integrate signal. When the conversion is ready, the charge in the DAC capacitors is dumped, preparing the TDC for the next cycle. The Integrate signal

33、is generated using a programmable frequency divider. During most of the frame transmission time, the frequency of the Integrate signal equals the symbol rate, thus taking one sample per symbol. However, during the symbol clock recovery process, see section IV, the TDCs sampling instant is shifted re

34、lative to symbol transitions by controlling the programmable divider. The AFE IC was implemented in a baseline 5 metal dual-well 140nm CMOS process. The chip photograph of the highly pad-limited IC is shown in Fig. 6. The PSK demodulator core (carrier recovery PLL and TDC) measures 370 x 210 m2 and

35、consumes 100A from a 1.8V supply in the highest data rate mode. IV. DIGITAL BASEBAND PROCESSING The FPGA-based DSP, see Fig. 3, retrieves the 8-bit TDC data accompanied by a data-valid signal, and the 13.56MHz recovered carrier as clock signal. The most relevant DSP functions are differential equali

36、zation (including PLL transfer equalization), symbol clock recovery, automatic gain correction (AGC) and non- linear adaptive equalization based on a channel estimator setting the coefficients of a decision feedback equalizer (DFE). In order to achieve low power consumption in the AFE as well as in

37、the DSP, the TDC samples the input signal at the absolute minimum rate of one sample per symbol. To make sure sampling is done close to the optimum instant, symbol clock recovery is done in closed loop with the AFE, controlling the TDCs programmable divider. All sample phase possibilities are scanne

38、d during a periodic pattern in the SOC, after which the option leading to lowest ISI is selected by the DSP algorithm. The DFE compensates for the ISI caused by the channel (typically dominated by the PCD antenna plus impedance matching network). The equalizer is adaptive as channel conditions are u

39、nknown a priori and vary depending on the relative antenna positions. Channel estimation is based on the (known) SOC sequence. The equalizer also compensates for non-linearities introduced by the supply- generation network on the AFE IC. The DSP design was mapped on a baseline 90nm CMOS process in o

40、rder to estimate power consumption. In that technology node, the predicted power was 300W. V. MEASURED RESULTS This section discusses measured results, first of the AFE stand-alone, followed by measurements done on the complete PSK receive chain. It should be noted that the AFE was powered with an e

41、xternal 1.8V supply since the supply generator did not support the current consumption of the 50 clock and ADC output buffers, that were present to drive the external FPGA board. The supply generation block, however, is always active to realistically load the antenna in a strongly non-linear fashion

42、. 241 Fig. 7. Measured INL and DNL of the TDC. Fig. 8. Measured phase noise of PLL + TDC chain. Measurement done at a sample rate of 3.39 MS/s (fc/4). The TDC integral and dynamic non-linearity (INL, DNL) are measured by applying two signals with a small frequency difference (corresponding to a phas

43、e ramp) at the two TDC input ports directly, bypassing the PLL with an on-chip debug multiplexer, and then capturing the TDC output codes. The input range was set to 57 (which is enough to handle the actual span when demodulating 60 PSK, taking into account PLL settling behavior), corresponding to a

44、n LSB size of 0.45 (92ps). Fig. 7 shows the resulting INL and DNL plots. The measured INL corresponds to 7.6 effective number of bits. The measured phase noise of the complete analog chain (consisting of carrier recovery PLL followed by the TDC) was measured by applying an unmodulated carrier at the

45、 AFE input and capturing the TDC output codes. Post- processing these, using the known TDC LSB size, results in the curves shown in Fig. 8. The black curve corresponds to the phase noise level at the AFE output; the gray curve is the phase noise level after having passed the differential decoder in

46、the DSP (at the equalizer input). This clearly shows the advantage of using differential PSK: the integrated phase noise drops from 1.0 rms to 0.3 rms due to the inherent low-frequency de-emphasis of the differential decoder. Fig. 9. Measured bit error rate versus PCD field strength. Finally, Fig. 9

47、 shows the measured bit error rate (BER) versus the transmitted magnetic field strength measured at 37.5mm from the PCD antenna, which was the distance of the PICC antenna to the PCD antenna in this measurement. Assuming (57,63) Hamming code is used for error correction, the target BER before correction was set at 210-4 (corresponding