Vivado从此开始（第2版）课件 6-Implementation - 10-IO-and-Clock-Planning

Lauren

GaoVivado

ImplementationNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaVivadoImplementation

Sub-processesopt_designpower_opt_designplace_designphys_opt_designroute_designwrite_bitstreamLogicOptimization(Optional)Power

OptimizationPlacement(Optional)Physical

SynthesisRoutingGeneratea

BitstreamNewFeature:

DirectivedirectivedirectiveCommandoptionto“direct”behaviortowrdalternate

goalDifferent

algorithmsDifferentobjectivesImplementationcommandswith

–directiveopt_design,place_design,

phys_opt_design,route_designAlternativeflowsto

useWhenthedefaultflowdoesnotmeetdesign

goalsWhentoolruntimeincreasecanbe

accommodatedUsesdifferent

algorithmsNotrandomseedslikeISEcost

tablesMoreconsistentandpredictable

behaviorHelp-opt_designtofindallthe

directives-directive

ExploreAllcommandshave–directive

ExploreISE

MAPISE

P&RISE

–effort_levelVivado

-directive-effort_levelhigh-directive

Explore-effort_levelhigh

-area_mode-directiveExploreArea(opt_design

only)-directive:Replacementfor

–effort_levelAutomaticmappingforallimplementation

commandsISE–effort_levelVivado-directive-effort_levelhigh-effort_level

medium-effort_levellow-effort_levelquick-directive

Explore-directive

Default-directiveRumtimeOptimized-directive

QuickNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaImplementation

StrategyDifferentdirectivesTools→options→StrategiesStrategiesaregroupedby

category–Performance,Area,Power,Flow,

CongestionStrategies

ExampleDesignflowPerformance_ExploreArea_ExplorePower_DefaultOptFlow_RunPhysOptCongestion_SpreadLogic_highopt_design√√√√√-directiveExploreExploreAreaDefaultDefaultDefaultpower_opt_design××√××place_design√√√√√-directiveExploreDefaultDefaultDefaultSpreadLogic_highpower_opt_design(post-place)×××××phys_opt_design√×√√√-directiveExploreDefaultExploreAggressiveFanoutOptroute_design√√√√MoreGlobalIterations-directiveExploreDefaultDefaultDefaultDirectives->commandlevel

behaviorStrategies->implementationrun-levelbehavior,acombinationofdirectivesDifferentstrategymay

haveDifferent

directivesVivadoimplementationdefault:-directiveareall

defaultPerformance_Explore:-directiveareall

ExploreDifferentdesign

flowsVivadoimplementationdefault:opt_design,place_design,

route_designPerformance_Explore:opt_design,place_design,phys_opt_design,

route_designEachstrategyhasdifferentdirectivesfortheimplcommandstepsYoucancustomizeyourown

strategyUserdefined

strategiesThePerformance_Explorestrategyisagoodfirstchoice,becauseitcoversalltypesofdesignsThePerformancestrategiesaimtoimprovedesignperformanceatthe

expenseof

runtimeStrategiescontainingthetermsSLLorSLRareforusewithSSIdevicesonlyImplementation

StrategyTcl

APITcl

APITcl

APIAllimplementationsub-processeshaveTcl

APItcl.pre:commandsshouldbeexecutedbeforethis

processtcl.post:commandsshouldbeexecutedafterthis

processExampleopt_design.tclNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaInProjectMode,theVivadoIDEallowsyou

toDefinemultipleimplementation

runsRunmultiplestrategiesonasingle

designCustomizeimplementationstrategiestomeetspecificdesign

requirementsSavecustomizedimplementationstrategiestouseinother

designsNon-ProjectModedoesnotsupportpredefinedimplementationrunsand

strategiesRunImplementationinProjectModewith

GUIlaunch_runs[-jobsarg][-scripts_only][-all_placement][-dirarg][-to_steparg][-next_step]

[-hostargs][-remote_cmd

arg][-email_toargs][-email_all][-pre_launch_script

arg][-post_launch_scriptarg][-force][-quiet][-verbose]runs...to_stepopt_design,power_opt_design,place_design,

power_opt_design(post_place)Phys_opt_design,route_design,

write_bitstream-to_step

place_design-to_step"power_opt_design

(Post-Place)"RunImplementationinProjectModewith

Tcllaunch_runsimpl_1launch_runsimpl_2-to_step

place_designcd

{F:\Vivado\Tutorial\logic_sim\XSim_Tutorial.runs\impl_2}open_checkpointsinegen_demo_placed.dcplaunch_runsimpl_2

-next_stepRunImplementationinNon-Project

ModeNon-projectbaseddesignsmustbemanuallymovedthrougheachstepoftheimplementationprocessusingTcl

commandsplace_design[-directivearg][-no_timing_driven][-unplace][-cellsargs][-post_place_opt][-quiet]

[-verbose]-post_place_optPotentiallyimprovecriticalpathtimingattheexpenseofadditional

runtimeThisoptimizationcanberunatanystageafterplacement,andcanbe

particularlyeffectiveonarouted

designTheoptimizationexaminestheworstcasetimingpathsandtriestoimproveplacementtoreduce

delayTheoptimizationisperformedonafullyplaceddesignwithtiming

violationsThe-directiveoptioncontrolstheoverallplacementstrategy,andisnotcompatiblewithanyspecificplace_design

options.place_designplace_designphys_opt_designroute_designplace_design-post_place_optroute_designroute_design[-unroute][-re_entrantarg][-netsargs][-physical_nets][-pinarg][-directivearg][-no_timing_driven][-preserve]

[-delay][-free_resource_mode]-max_delayarg-min_delayarg[-quiet]

[-verbose]-preservePreserveexisting

routing-delayUsewith-netsor-pinoptiontorouteindelaydriven

mode-max_delayUsewith-pinoptiontospecifythemax_delayconstraintonthe

pin-min_delayUsewith-pinoptiontospecifythemax_delayconstraintonthe

pinroute_designroute_design-delay-nets$myCriticalNetsroute_design-preserve-directiveRuntimeOptimizedroute_design-unroutephys_opt_design[-fanout_opt][-placement_opt]

[-rewire][-critical_cell_opt][-dsp_register_opt]

[-bram_register_opt][-bram_enable_opt][-shift_register_opt][-hold_fix]

[-retime][-force_replication_on_netsargs][-directivearg]

[-critical_pin_opt][-quiet]

[-verbose]Commandoptionslimittheoptimizationscopetoonlythespecifiedoptions–Oneoptionper

optimizationphys_opt_designTiming-drivenoptimizationsincludedby

defaultFanout:replicatedriversofhighfanout

netsPlacement:move

cellsRewiring:restructurelogic

conesCriticalcells:replicatecriticalpath

cellsDSPregisters:moveregistersto/from

DSPBRAMregisters:moveregistersto/from

BRAMShiftregisters:moveregistersfrom

SRLsCriticalpins:swapphysicalLUTinput

pinsVeryhighfanout:replicatedriversofvery-highfanout

netsBRAMenable:improvepower-optimizedBRAM

enablesPage

20WhatOptimizationsare

Performed?Optional

optimizationsForcednetreplication:replicateregardlessoftiming

slackRegisterretiming:balanceregistersacrosscombinational

delaysHold-fix:insertdatapath

delayPage

21WhatOptimizationsare

Performed?Differentstrategymayhavedifferentdesignflowswith

differentdirectivesDirectiveisincompatiblewithotheroptionsinopt_design,place_design,phys_opt_designand

route_designDirectivesandstrategiesprovidealternateflowstotrywhenthe

tooldefaultsdon’tmeettimingondifficult

designsSomeTclcommandcanhelptomeet

timingplace_design

–post_place_optphys_opt_designroute_design–delay

–netsPerformance_Exploreishelpfulfortiming

closureSummaryLauren

GaoIncremental

ImplementationBasicIncrementalCompile

FlowRunningIncrementalCompileinProjectModeandNon-ProjectModeAdvancedAnalysisforIncremental

CompileDemoAgendaIncrementalCompile

FlowRTL

ChangeNetlist

ChangeRevisedRTLSynthesisRevisedNetlistIncrementalPlace&

RouteRevisedCheckpointReferenceRTLSynthesisReferenceNetlistNormalPlace&

RouteReferenceCheckpointIncrementalRunWhenLess

than

5%changein

cells➔

3x

speedup

in

P&R

runtimeWhySave

runtimeMorepredictableresultsFastertiming

closureWhenandWhytoUseIncremental

FlowReuseexistingdesigndataaftersmallRTL

changesDonotusetheincrementalflowaftermajordesign

changesReference

designAnearlieriterationorvariationofthecurrent

designIthasbeensynthesized,placedand

routedWhatweuseasreferenceis

<_routed.dcp>Current

designThecurrentdesignincorporatessmalldesignchangesorvariationsfromthereferencedesignThesechangesorvariationscan

includeRTL

changesNetlist

changesBothRTLchangesandnetlist

changesReferenceDesign&Current

DesignRunningIncrementalPlaceand

Route??matchPlace:reusematching

cellsRoute:reusematching

netsReference

DesigncellnetCurrent

Designcellnetthefollowingcanhavealargeimpactonincrementalplacement

androuting

runtimeImpactofsmallRTLchanges:thefollowingcanleadtoverylargechangesinthesynthesized

netlistIncreasingthesizeofaninferred

memoryWideninganinternal

busChangingdatatypesfromunsignedto

signedImpactofchangingconstraintsandsynthesis

optionsChangingtimingconstraintsand

resynthesizingPreservingordissolvinglogical

hierarchyEnablingregister

re-timingEffectivelyReusingPlacementand

RoutingOriginalRunandNewRunReferenceDesignCurrentDesignsynth_1impl_1synth_2impl_2CreateNew

Runsynth_1impl_1impl_2RTL

ChangesNetlist

ChangesCreateNew

RunBothrunshavethesame

strategy-directivecannotbeusedinincremental

modephys_opt_designdoesnothaveanincremental

modeImplementationsettings→incremental

compileSelecttherunandapplyareference

checkpointAfterselectincrementalcompile,itcanbeshowninrun

propertyUsingIncrementalCompileinProject

Modeset_propertyINCREMENTAL_CHECKPOINTreference.dcp[get_runs

impl_2]UsingIncrementalCompileinNon-Project

Mode#readrevised

designlink_design-part$my_part-top$revised_topopt_designread_checkpoint-incremental

$ref.dcpplace_design#ifruninoriginal,reference

runphys_opt_designroute_designreport_incremental_reuse-file

routed_reuse.rptreport_timing_summary-label_reused-max_paths10

\–filerouted_ts.rptIncrementalReuse

ReportPage

12report_timing

-no_reused_labelAdvanced

Analysis默认情况下会标记复用信息如果不希望标记复用信息，使用此命令Advanced

Analysisget_propertyINCREMENTAL_CHECKPOINT[current_run]reset_propertysetmyreused_cells[get_cells-hier-filter"IS_REUSED==

TRUE"]report_property[lindex$myreused_cells0]setmyreused_nets[get_nets-hier-filter"IS_REUSED==TRUE"]report_property[lindex$myreused_nets

0]setmyreused_pins[get_pins-hier-filter"IS_REUSED==

TRUE"]report_property[lindex$myreused_pins

0]setmyreused_ports[get_ports-hier-filter"IS_REUSED==

TRUE"]report_property[lindex$myreused_ports0]DemoLauren

GaoFiveMostCommonly

UsedTclCommandsin

VivadoBasicconceptofobjectsin

VivadoHowtousefivemostimportantTclcommandsin

design–get_cells,get_nets,get_ports,get_pins,

get_clocksAgendaObjectsinVivado:cell,port,netand

pincellcellcellcellnetpinportpackage

pinIO

bankcellBasicCommands

get_*Command-hierarchical-regexp-nocase-filter-of_objectsget_cells√√√√√get_nets√√√√√get_pins√√√√√get_portsX√√√√get_clocksX√√√√-hierarchical→

-hier-of_objects→

-of-filter:usingpropertiesto

filter1.)3.)Booleantype

propertiesString

Comparisonequal==not

equal!=match=~not

match!~2.)Multiplefilter

expressionsAND(&&),OR

(||)① get_ports-filter{DIRECTION==IN&&NAME!~

"*RESET*"}② -filter{IS_PRIMITIVE&&

!IS_LOC_FIXED}③ get_cells-hier{*State*

*reg*}④ get_cells→get_cells

*-of_objectscellpinnetpincellclocknetTPnetcellpinportclockportcellnetclockTPclockpinnetportIOBankPPinPPinIOBankportportsiteTP:timingpathPpin:Package

pinObjectRelationshipsinVivadoDesign

SuitecellpinportclocknetExample:get_cells-of[get_nets-of[get_pins-of[get_cellswbDataForInput_IBUF_inst]-filter{DIRECTION==OUT}]]wbDataForInputReg_regvalidForEgressFifo_reg[0]_i_1

wbDataForInput_IBUF_instIO

bankPackage

Pin-of_objects

ExamplesGetthepinsofthisblue

cellget_pins-of[get_cellsdemuxState_reg]demuxState_reg/CdemuxState_reg/CEdemuxState_reg/RSTdemuxState_reg/Q

demuxState_reg/DGetcellbythegivenpin

Dget_cells-of[get_pinsdemuxState_reg/D]demuxState_regGetcellconnectingtothegivennet

wbClkget_cells-of[get_nets

wbClk]-of_objects

ExamplesGetnetsconnectingtothegiven

cellget_nets-of[get_cells

demuxState_reg]wbClkdemuxState1_outresetdemuxState

demuxState0_outGetnetconnectingtothegivenpin

Dget_nets-of[get_pins

demuxState_reg/D]demuxState0_outGetclocksconnectingtothegivenpinCget_clocks-of[get_pins

demuxState_reg/C]wbClk-of_objects

ExamplesGetportsconnectingtothegivenclock

wbClkget_ports-of[get_clockswbClk]wbClkGetcellsconnectingtothegiven

netget_cells-of[get_netsdemuxState0_out]demuxState_reg

demuxState_iQuestionsWhat’sthe

answer?IfwewanttogetthecelldemuxState_regbythenetdemuxState0_out,what’s

thetclcommand?get_cells-of[get_netsdemuxState0_out]get_cells-of

\[get_pins-of[get_netsdemuxState0_out]-filter

"DIRECTION==IN"]-hierarchical

ExplanationstopBAA1

A2

B1

B2#theprincipleof

-hierarchicalsetresult

{}foreachhcell[list""ABA/a1A/a2B/b1B/b2]{current_instance$hcell;#Movescopeto$hcellsetresult[concat$result[get_cells<pattern>]]current_instance;#Returnscopetodesigntop-level}matchthespecifiednamepatternateachlevelofthedesignhierarchy,andnotagainstthefullhierarchicalnameofan

objectThe

specified

search

pattern

must

not

include

the

hierarchical

separator

otherwise

no

object

willbe

returnedWhen-hierarchicalisusedwith-regexp,thespecifiedsearchstringismatchedagainstthefullhierarchical

nameget_cells{A*

B*}get_cells–hier{A*

B*}get_cells

B/*get_cells–hier

B/*get_cells–hier–regexp

B/.*get_cells–hier–filter

{NAME=~*B*}get_cells–hier–regexp

.*B.*A

BAA/A1A/A2BB/B1

B/B2B/B1

B/B2Nocellsmatched

‘B/*'B/B1

B/B2BB/B1B/B2BB/B1B/B2B/B2I/OPortPropertiesforScalar

PortsNAME:Itisconsistentwiththatdescribedinsource

codeDIRECTION:INOUTor

INOUTPACKAGE_PIN:portspinlocationIOBANK:portsbank

locationUNCONNECTED:1or

0get_ports-filter{DIRECTION==IN}get_ports-filter{IOSTANDARD==LVCOMS18}get_ports-filter{UNCONNECTED==1}get_ports-filter{PACKAGE_PIN==""}get_ports-filter

{IOBANK==34}I/OPortPropertiesforBus

PortsNAME,

BUS_NAMEBUS_WIDTHBUS_DIRECTIONget_ports-filter{BUS_NAME!=

""}I/OBankandPackagePin

Propertiesget_package_pinsget_iobanksget_iobanks-of[get_portsreset]get_package_pins-of[get_portsbftClkget_package_pins-of[get_iobanks

34]Example:GetIOshaving"Data"stringintheir

names:get_ports*data*GetinputportswithIOstandards

LVCOMS18:get_ports-filter{DIRECTION==IN&&

IOSTANDARD==LVCMOS18}setmyinport[all_inputs]setmyport[filter$myinport

{IOSTANDARD==LVCMOS18}]GetIObankwhereH4is

located:get_iobanks-of_objects[get_package_pins

H4]Workingwith

Cellscurrent_instance:Setthecurrentinstanceinthedesignhierarchytothespecifiedinstancecellortothetop

moduleget_cells:Getsalistofcellobjectsinthecurrentdesignthatmatch

aspecifiedsearch

patternREF_NAME:In

verilog:modulecounterIn

VHDLentitycounter

isNAME:Instantiationnamewith

hierarchyget_cells-quiet

–hierarchical\-filter{REF_NAME=~FD*}

*rd_*get_cells-quiet

–filter\{REF_NAME=~

FD*}\egressLoop[0].egressFifo/buffer_fifo/*Ifthecellinthetoplevel,PARENTwillbe

empty.PropertiesofFDCEand

LUTExamplesGetcellsin

arnd1get_cellsarnd1/*current_instance-quiet[get_cellsarnd1];sethb1_cells[get_cells*]current_instance-quietGetblackboxandprimitivecellsintop

levelsetall_top_level_blocks[get_cells

*]sethierb_list[filter-quiet

$all_top_level_blocks

{IS_BLACKBOX ==0

&&

IS_PRIMITIVE ==0}]setprimitive_list[filter-quiet

$all_top_level_blocks

{IS_BLACKBOX ==0&&IS_PRIMITIVE==

1}]setblackb_list[filter-quiet

$all_top_level_blocks

{IS_BLACKBOX ==1&&IS_PRIMITIVE==

0}Getallsequentialcellsfromentiredesignandreportits

REF_NAMEsetlist_seq_cells[get_cells

-hierarchical

-filter {IS_SEQUENTIAL==1}*]set

list_seq_type [get_propertyREF_NAME

$list_seq_cells]Getpropertyandchange

itget_propertyINIT[get_cells

A/B/data_reg]Set_propertyINIT1’b0[get_cells

A/B/data_reg]get_nets:Getsalistofnetsinthecurrentdesignthatmatchaspecifiedsearch

pattern-segments:Getallthesegmentsofahierarchicalnet,acrossalllevelsof

thehierarchy-boundary_type:Getsthenetsegmentatthelevelofaspecifiedhierarchicalpin.Values:upper,lowerandboth.Default:

upperWorkingwith

NetsQABOnlyB/weis

obtainedget_nets

B/weA/weweB/weareall

obtainedget_nets–segmentB/weGetnet

‘we’get_nets

–boundary_typeupper

\–of[get_pins

B/we_i_pin]Set

propertyset_propertyMARK_DEBUGtrue[get_net

{controladdr}]we DWorkingwith

PinsMMCMRSTU0get_pins:Getsalistofpinobjectsinthecurrentdesignthatmatchaspecifiedsearch

pattern–-leaf:Includeleafpins,fromprimitiveorblackboxcells,fortheobjects

specifiedwiththe-of_object

argumenti_clk_genresetresetrst_IBUF_instI Osetmynet[get_netsi_clk_gen/U0/reset]setmypina[get_pins–leaf–of$mynet]setmypinb[get_pins–of

$mynet]puts“Leafpins:

$mypina”puts“Pins:

$mypinbLeafpins:i_clk_gen/U0/mmcm_adv_inst/RSTrst_IBUF_inst/OPins:i_clk_gen/U0/mmcm_adv_inst/RST

i_clk_gen/U0/resetget_selected_objects:GetstheobjectscurrentlyselectedintheVivadoIDEselect_objects:SelectsthespecifiedobjectintheappropriateopenviewsintheGUI

modeunselect_objects:Unselectsthespecifiedobjectorobjectsthat

werepreviouslyselectedbytheselect_objects

commandWorkingwithSchematic

ViewerBefore

select

objects,

you

should

unselect

the

previous

one

firstly

unselect_objects-quiet

[get_selected_objects]select_objects[get_cells

i_simdatactrl]Afterreport_timing_summary,

slackcanbe

shown Workingwith

Clocksreport_clock_interactionReportoninterclocktimingpathsandunclocked

registersreport_clock_networksReportclock

networksreport_clock_utilizationReportinformationaboutclocknetsin

designreport_clocksReport

clocksget_clocksGetalistofclocksinthecurrent

designall_clocksGetalistofallclocksinthecurrent

designget_generated_clocksGetalistofgeneratedclocksinthecurrent

designcreate_clockCreateaclock

objectcreate_generated_clockCreateageneratedclock

objectget_clocks{*clock*ck

*Clk}get_clocks-include_generated_clockswbClkreport_property-all[get_clockswbClk]get_clocks-of[get_pins

{i_firctrl/raddrcoe_i_reg[3]/C}]get_clocks-of[get_netsi_firctrl/CLK]get_clocks-filter

{PERIOD<20.0}netpinClocknet:clock

netpin:clock

pinFiveTclcommandsarewidelyused

inTiming

constraintsTiming

analysisDebuggingTheycanbeused

underElaborateddesignSynthesized

designImplemented

designSummaryLauren

GaoProgrammingand

DebuggingChangingDeviceConfigurationBitstream

SettingsUsingtheNetlistInsertionMethodforDebuggingaDesigninVivadoUsingtheHDLInstantiationMethodforDebuggingaDesigninVivadoUsingaVIOCoreforDebuggingaDesignin

VivadoUsingTcltoCreateDebugUnitDemoAgendaChangingDeviceConfigurationBitstream

SettingsUsingtheNetlistInsertionMethodforDebuggingaDesigninVivadoUsingtheHDLInstantiationMethodforDebuggingaDesigninVivadoUsingaVIOCoreforDebuggingaDesignin

VivadoUsingTcltoCreateDebugUnitDemoAgendaChangingDeviceConfigurationBitstream

SettingsISE:Generate

Programming

File ➢Vivado:topnetlist→Add

property→Process

PropertiesChangingDeviceConfigurationBitstream

SettingsUsingtheNetlistInsertionMethodforDebuggingaDesigninVivadoUsingtheHDLInstantiationMethodforDebuggingaDesigninVivadoUsingaVIOCoreforDebuggingaDesignin

VivadoUsingTcltoCreateDebugUnitDemoAgendaVivadoDebug

CoreVivadoDebug

CoreIBERTILAJTAGtoAXI

MasterVIOTwoMethodstoAddDebugCoreinthe

DesignUsingtheHDLInstantiation

MethodUsingtheNetlistInsertion

MethodHDLSource

CodeSynthesisImplementationProgram&DebugOpenHardware

ManagerVivadoLogic

AnalyzerNetlistinsertionmethodisrecommendedGenerate

BitstreamUsingtheNetlistInsertion

MethodSynthesizingthe

DesignProbingandAddingDebug

IPSynthesis

settings:-flatten_hierarchynonerebuiltHowtofindtarget

netsInHDLsource

codeInNetlist

viewInSchematic

viewMarkingHDLSignalsforDebug

(Pre-Synthesis)ForanRTLnetlist-based

projectVivado:

VHDL/Verilogattributemark_debug:string;attributemark_debugofchar_fifo_dout:signalis

"true";(*mark_debug="true"*)wire[7:0]

char_fifo_dout;Synplify:

VHDL/Verilogattributesyn_keep:boolean;attributemark_debug:

string;attributesyn_keepofchar_fifo_dout:signalis

true;attributemark_debugofchar_fifo_dout:signalis

"true";(*syn_keep="true",mark_debug="true"

*)wire[7:0]char_fifo_dout;MarkingNetsforDebugintheSynthesizedDesign(Post-Synthesis)Forasynthesizeddesign(Opensynthesizeddesign

firstly)Netlistview→Selectnet

→Rightclick→Mark

DebugSchematicview→Selectnet

→Rightclick→Mark

DebugNetlist/Schematicview→Select

net→DraggingintoUnassigned

DebugNets

folderYoucanuseget_netsinconjunctionwithotherget_*tofindyour

targetnets

effectivelyUsingTcltoSetmark_debug

AttributeForasynthesizeddesign(Opensynthesizeddesign

firstly)set_propertymark_debugtrue[get_nets

sine*]Confirmget_netsas

expectedselect_objects[get_nets

sine*]F4Usethismethodinsynthesizeddesigns

onlyChangingDeviceConfigurationBitstream

SettingsUsingtheNetlistInsertionMethodforDebuggingaDesigninVivadoUsingtheHDLInstantiationMethodforDebuggingaDesigninVivadoUsingaVIOCoreforDebuggingaDesignin

VivadoUsingTcltoCreateDebugUnitDemoAgendaInHDLsourcecode,use“KEEP”or“DON’T_TOUCH”toavoid

targetsignalsbeing

optimizedGetaprobelist.Eachprobeconnectstoonesignal.Theyhavethe

samewidthGenerateILAipcoreandaddittotheprojectInstantiatetheILAinHDLsource

codeUsingtheHDLInstantiation

Methodattributekeep:string;attributekeepofsineSel:signalis

"true";attributekeepofsine:signalis

"true";Where

isICON?Vivadocanautomaticallygeneratedbg_hubaftergeneratingILAICONisreplacedbydbg_hubwhichiseasyto

useMigratefromICONto

dbg_hubChangingDeviceConfigurationBitstream

SettingsUsingtheNetlistInsertionMethodforDebuggingaDesigninVivadoUsingtheHDLInstantiationMethodforDebuggingaDesigninVivadoUsingaVIOCoreforDebuggingaDesignin

VivadoUsingTcltoCreateDebugUnitDemoAgendaVirtualInput/Output(VIO)

coreBothmonitoranddriveinternalFPGAsignalsinreal

timeSynchronoustothedesignbeing

monitoredand/or

drivenCanonlybeusedwithHDLsource

codeVIOChangingDeviceConfigurationBitstream

SettingsUsingtheNetlistInsertionMethodforDebuggingaDesigninVivadoUsingtheHDLInstantiationMethodforDebuggingaDesigninVivadoUsingaVIOCoreforDebuggingaDesignin

VivadoUsingTcltoCreateDebugUnitDemoAgendaUsingTcltoCreateDebug

Unitcreate_debug_coreu_ila_0

labtools_ila_v3set_propertyport_width1[get_debug_portsu_ila_0/clk]connect_debug_portu_ila_0/clk[get_nets[listclk]]set_propertyport_width2[get_debug_portsu_ila_0/probe0]connect_debug_portu_ila_0/probe0\[get_nets[list{sel[0]}{sel[1]}]]create_debug_portu_ila_0probeset_propertyport_width2[get_debug_portsu_ila_0/prob