版权说明:本文档由用户提供并上传,收益归属内容提供方,若内容存在侵权,请进行举报或认领
文档简介
1、Lesson 3FPGA Programming BasicsIntroductionDefining FPGA Logic with LabVIEWFPGA VI Development Process Developing the FPGA VIFront Panel CommunicationTesting with the EmulatorCompiling the FPGA VIA. IntroductionFPGA Layout and ComponentsHow FPGA WorksProgrammable interconnect switches and wires rout
2、e signals in an FPGA.Switches are known as Register Flip-Flops.Flip-Flops pass data on a rising edge of the clock.Compiled LabVIEW code produces a Look-up Table (LUT).LUT defines the interconnections between configurable logic blocks (CLBs).How FPGA Works (continued)Implements a VI that calculates a
3、 value for F from inputs A, B, C, and D where F = CD(A + B)Hardware ComparisonsMost important specification is number of logic slicesSlices help to represent the amount of logic that can implemented on a single FPGAWays to conserve FPGA space are covered in more detail in Lesson 8: FPGA Optimization
4、FPGA Family SpecificationsComponent Type1M Gate FPGA(PCI-7831R)3M Gate FPGA(PCI-7833R)Equivalent number of logic cells11,52032,256Number of logic slices 5,12014,336Available embedded RAM (bytes)81,920196,608B. Defining FPGA Logic with LabVIEWFPGA ModuleDo not have to learn VHDLTrue parallel executio
5、nDeterministicCompiling LabVIEW VIs to FPGA HardwareConvert the FPGA VI into executable codeFPGA Module compiles VIGraphical code translated to VHDL Xilinx ISE compiler creates circuit from VHDLCompiler optimizes the implementationA bitstream file resultsBitstream loads at run timeBitstream reloads
6、at power-upOn-board flash memoryController over PCI BusBenefits of FPGA Logic in LabVIEWFPGA provides:TimingTriggeringProcessingCustom I/OEach fixed I/O uses a portion of the FPGA logicThe PCI interface also uses a portion of the FPGA logicC. FPGA VI Development ProcessKeep in mindNo operating syste
7、m on the FPGADownload and run one top-level VI at a time FPGA can run independently of the hostFPGA can store dataEditing a VI in the FPGA Target activates the FPGA paletteInteger math and fixed-point mathD. Developing the FPGA VIFPGA is fast and reliableFPGA has limited space FPGART and/or PCTime c
8、ritical controlExtensive analysisAcquisitionFile I/OTiming in the FPGA User interfaceIn-line processingSupervisory controlTriggeringAdd a VI Under the FPGA TargetDemonstrationCreate an FPGA VI and explore the Functions palette supported under FPGA.E. Front Panel CommunicationFPGA Front PanelUse simp
9、le controls and indicatorsUse controls and indicators only when the value will be needed on the hostUse temporary controls and indicators for debuggingInteractive Front Panel CommunicationInteractive Front Panel Communication (continued)FPGA has no user interfaceMust communicate data from FPGA to ho
10、st PCRequires no additional programmingFront panel displays on host PCBlock diagram executes on FPGA as compiledCommunication layer shares all control and indicator valuesCannot use debugging tools when running FPGA VITest with Emulator first, or add indicators as probesF. Testing with the EmulatorC
11、ompilingfew minutes to several hoursVerify logic before compilingLabVIEW bit-accurate emulation modeExecutes logic on the Windows PCTraditional debugging tools are availableTwo kinds of emulationRandom data for inputsTarget hardware for I/OUsing the EmulatorRight-click the FPGA Target in the Project
12、 Explorer window and select Properties.Select General.Select an Emulator option.Click OK.Run the VI.*Set the Emulator to Off after testExercise 3-1: Creating a LabVIEW FPGA VICreate a VI that adds two numbers and runs a benchmark in parallel that determines how fast code is running.Run the VI in emu
13、lation mode and use debugging tools.G. Compiling the FPGA VIClick RunConverts graphical code to VHDLGenerates intermediate filesCompiling VI for FPGA Dialog Box Disconnect Disconnects from the Compile Server so that you can continue working in LabVIEWFollow instructions in the dialog box to reconnec
14、tLabVIEW FPGA Compile Server Dialog BoxToolsFPGA ModuleStart Local Compile Server to view previous compile reportsClick Compile ListSuccessful Compile ReportExercise 3-2: Compile a LabVIEW FPGA VICompile the application created in Exercise 3-1.SummaryQuiz1.The FPGA VI runs in an operating system on the FPGA processor.a.Trueb.False2.You must know VHDL programming to reconfigure the FPGA.a.Trueb.FalseSummaryQuiz3.The FPGA can achieve t
温馨提示
- 1. 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。图纸软件为CAD,CAXA,PROE,UG,SolidWorks等.压缩文件请下载最新的WinRAR软件解压。
- 2. 本站的文档不包含任何第三方提供的附件图纸等,如果需要附件,请联系上传者。文件的所有权益归上传用户所有。
- 3. 本站RAR压缩包中若带图纸,网页内容里面会有图纸预览,若没有图纸预览就没有图纸。
- 4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
- 5. 人人文库网仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对用户上传分享的文档内容本身不做任何修改或编辑,并不能对任何下载内容负责。
- 6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
- 7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。
最新文档
- 2024年人教版七年级英语下册第八单元课堂练习题及答案第1课时 Section A(1a-1c)
- 高考物理大一轮复习 课后限时集训18 动量和动量定理-人教版高三全册物理试题
- 高考生物一轮复习 第一编 考点通关 考点 基因的分离定律练习(含解析)-人教版高三全册生物试题
- 课堂效果调查问卷
- 护士“三基”理论培训考核试题及答案
- 2024届江西省八所重点中学高三下学期4月联考生物答案
- 2024届上海市黄浦区高考二模物理卷参考答案
- 浙江省杭州市萧山区2023-2024学年八年级下学期期中数学试题
- 互联网租赁自行车智能终端校准规范
- 2024年人教版七年级英语下册第六单元 第4课时 Section B (1a-1d)
- (2024)保密观在线培训单位考试题库及参考答案
- 教科版科学三年级下册第一单元《 物体的运动》测试卷含完整答案【易错题】
- 空气能热水器安装合同范本合同模板
- 7天试用期协议书
- 合肥市45中2024届中考三模历史试题含解析
- SMT-快速换线推进报告-.课件11
- 合肥市第六中学2024年高考化学二模试卷含解析
- 管理人员具备的十大能力.ppt
- GB-T-12469-1990-焊接质量保证-钢熔化焊接头的要求和缺陷分级.pdf
- GA 1166-2014 石油天然气管道系统治安风险等级和安全防范要求
- 多功能跑步机英文资料
评论
0/150
提交评论