基带板原理图设计文档

1、基带板原理图设计文档1、 系统框图根据与41所沟通，系统框图如下，基带板与rf、主控板、时序板、中频rx和中频tx板的连接关系如下，为了实现lte基带处理的各种功能和与其他各个处理板的数据交换和接口需要，进行了基带板原理图设计。2、 功能要求：基带板要完成的功能包括：协议软件的处理、物理层软件的处理、系统定时和对rf的控制数据处理。为了完成这些内容，系统包含arm、dsp和fpga三个主要器件，其中arm完成协议软件处理、dsp负责处理物理层软件中的部分内容、fpga完成系统定时和物理层算法的部分内容。3、 系统框图arm:完成操作系统及协议、应用等功能，其支持的借口比较丰富；接口描述：dra

2、m controller：ddr ram；srom controller：flash，与dsp、fpga共用，用于boot代码的存储；fpga上的ram，预留，防止协议中有算法需要用硬件实现；双端口ram1，用于与dsp交换数据；双端口ram2，用于与41所应用板交换数据；i2c：用于power、clk芯片的控制；i2s：用于codic和blue tooth；spi：与fpga间发送控制信息；uart：用于trace;usb：用于应用；gpio：用于与fpga和dsp之间产生硬件中断；jtag：调试接口；dsp:完成物理层流程及算法；emifa：flash，与arm、fpga共用，用于boot

3、代码的存储；fpga上的ram，用于与fpga数据交换；双端口ram1，用于与arm交换数据；ddr2：ddr ram；i2c：与fpga相连，用于交换控制信息；mcbsp0：用于codicmcbsp1：与fpga相连，用于交换数据信息；rapid io：与fpga相连，用于交换数据信息；gpio：用于与fpga和arm之间产生硬件中断；fpga:完成系统定时、射频数据的接收及部分物理层算法；pci：用于与射频交换数据，需要确认。4、时钟设计let要求的采样时钟：122.88mhzarm工作时钟：12mhz，可以通过外部的晶振提供或外部的时钟提供；27mhz，用于其中的某些模块，可以选择是否使

4、能；32.768khz，看门狗时钟；dsp工作时钟：clkin1：33.366.6mhz 选50mhzclkin2：12.526.7mhz 选25mhzemifclk：160或200 mhz 选 200 mhzsrio clk：125或156.25或312.5 mhz 选择 125mhz备156.25mhz系统时钟为20mhz，通过ti的cdce937产生dsp和arm的输入时钟outfreqy120mhzto fpgay225mhzdsppll1y3125mhzsrioy450mhzdsppll2y5200mhzdsp_emifay612mhzarmy748mhzy8122.88 mhzlt

5、e tofpgay9122.88 mhz考虑到板子单独使用和与41所接口使用的情况：单独使用安上述设置使用与41所接口使用时，系统时钟由41所射频板提供，时钟为122.88mhz，经过cpld分频后得到15.36mhz的时钟，再输出到cdce946后产生相应的其他时钟，输入为：outfreqy225mhzdsppll1y3125mhzsrioy450mhzdsppll2y5200mhzdsp_emifay612mhzarmy748mhzsrio clk：125或156.25或312.5 mhz 选择 125mhz 备156.25mhz5电源设计需求：6410电源种类：1.2、1.8v、2.5v

6、、3.3vsignal i/o description voltage 推荐值选择值vddalive p internal power for alive block 1.2 1.2vddarm p internal power for arm1176 core and cache 1.1/1.2 1.2vddint p internal power for logic 1.2 1.2vddmpll p power for mpll core 1.2 1.2vddapll p power for apll core 1.2 1.2vddepll p power for epll core 1.

7、2 1.2vddotg p power for usb otg phy 3.3 3.3vddotgi p internal power for usb otg phy 1.2 1.2vddmmc p io power for sdmmc 1.83.3 3.3vddhi p io power for host i/f 1.83.3 3.3vddlcd p io power for lcd 1.83.3 3.3vddpcm p io power for pcm (audio i/f i2s, ac97) 1.83.3 3.3vddext p io power for external i/f (u

8、art, i2c, camera i/f, etc.) 1.83.3 3.3vddsys p io power for system control. (clock, reset, operation mode, jtag, etc) 1.83.3 3.3vdduh p power for usb host 3.3 3.3vddadc p power for adc core and io 3.3 3.3vdddac p power for dac core and io 3.3 3.3vddrtc p power for rtc logic and io 1.83.0 2.5vddm0 p

9、io power for memory port 0 1.83.3 3.3vddss p io power for ata io muxed in mem0 port 1.83.3 3.3vddm1 p io power for memory port 1 1.8/2.5 1.86455电源种类：1.2v、1.8v、3.3vsignal i/o description voltage 推荐值选择值vrefsstla(dvdd18/2)-v reference for sstl buffer (ddr2 memory controller). this inputvoltage can be g

10、enerated directly from dvdd18 using two 1-kw resistors to forma resistor divider circuit.1.8v/2vrefhstla(dvdd15/2)-v reference for hstl buffer (emac rgmii). vrefhstl can begenerated directly from dvdd15 using two 1-kw resistors to form a resistordivider circuit.1.5v/2dvddrs1.8-v i/o supply voltage.（

11、srio regulator supply）1.8v1.8avddaasrio analog supply:1.25-v i/o supply voltage (-1000 and -1200 devices)1.2-v i/o supply voltage (-850 and -720 devices).do not use core supply.1.25v1.2v1.2avdll1a1.8-v i/o supply voltage.1.8v1.8avdll2a1.8-v i/o supply voltage.1.8v1.8dvddrmssrio interface supply:1.25

12、-v core supply voltage(-1000 and -1200 devices)1.2-v core supply voltage (-850 and -720 devices).the source for this supply voltage must be the same as that of cvdd1.25v1.2v1.2dvdd12smain srio supply:1.25-v i/o supply voltage (-1000 and -1200 devices)1.2-v i/o supply voltage (-850 and -720 devices).

13、do not use core supply.1.25v1.2v1.2avddtasrio termination supply:1.25-v i/o supply voltage (-1000 and -1200 devices).1.2-v i/o supply voltage (-850 and -720 devices).do not use core supply.1.25v1.2v1.2dvdd15s1.8-v or 1.5-v i/o supply voltage for the rgmii function of the emac.1.8v1.5v1.8dvdd18s1.8-v

14、 i/o supply voltage (ddr2 memory controller)1.8v1.8dvdd33s3.3-v i/o supply voltage3.3v3.3cvdds1.25-v core supply voltage (-1000 and -1200 devices).1.2-v core supply voltage (-850 and -720 devices).1.25v1.2v1.2fpgasignal i/o description voltage vccaux2.5vccint1.0vcco电源选择：fpga：vccaux2.53atps74401vccin

15、t1.010apth04t240wvcco3.310apth04t240w1.86apth08t230w/tps51100dsp、arm1.2tps650511.8pth08t230w3.3pth04t240w1.25pth04t240w6、fpga模式选择：configuration mode m2:0 bus width cclk direction master serial 000 1 output master spi001 1 output master bpi-up010 8, 16 output master bpi-down011 8, 16 output master se

16、lectmap100 8, 16 output jtag 101 1 input (tck) slave selectmap 110 8, 16, 32 input slave serial 111 1 input 我们系统中选择jtag或slave selectmap，所以m2固定为高，m1:0为01则为jtag，为10即为slave selectmap，为11则为slave serialslave selectmap模式下：可以设置为dsp boot 还是arm boot，需要的信号：cclk： 写使能cs_b： 片选rdwr_b：gpioslave serial模式下：可以设置为dsp

17、boot 还是arm boot，cclk： gpiod_in： gpio7、dsp设置：aea19/bootmode3aea18/bootmode2aea17/bootmode1aea16/bootmode0设置boot模式：0000 - no boot (default mode)0001 - host boot (hpi)0010 -reserved0011 - reserved0100 - emifa 8-bit rom boot0101 - master i2c boot0110 - slave i2c boot0111 - host boot (pci)1000 thru 1111

18、- serial rapid i/o boot configurationscfggp2:0 pins must be set to 000b during reset for proper operation of the pci boot mode.aea15/aeclkin_sel0 emifa 输入时钟选择0 - aeclkin (default mode)1 - sysclk4 (cpu/x) clock rate. the sysclk4 clock rate is software selectable via the software pll1 controller. by d

19、efault, sysclk4 isselected as cpu/8 clock rate.aea14/hpi_width1hpi总线宽度选择0 - hpi operates as an hpi16 (default). (hpi bus is 16 bits wide. hd15:0pins are used and the remaining hd31:16 pins are reserved pins in thehi-z state.)1 - hpi operates as an hpi32.aea13/lendian设置 device endian mode (lendian)0

20、- system operates in big endian mode1 - system operates in little endian mode(default)aea12/utopia_en1utopia enable bit (utopia_en)utopia peripheral enable(functional)0 - utopia disabled; ethernet mac (emac) and mdio enable(default).emac/mdio configuration (interface)mii, rmii, gmii or the standalon

21、e rgmii is controlled by themacsel1:0 bits.1 - utopia enabled; emac and mdio disabled except when the macsel1:0 bits = 11 then, the emac/mdio rgmii interface is still functional.and if macsel1:0 = 11, the rgmii standalone pin functions can be used.aea111必须接1k下拉电阻aea10/macsel1aea9/macsel0emac/mdio in

22、terface select bitsaea8/pci_eeai0aea8: pci auto-initialization via external i2c eepromif the pci peripheral is disabled (pci_en pin = 0), this pin must not bepulled up.0 - pci auto-initialization through i2c eeprom is disabled (default).1 - pci auto-initialization through i2c eeprom is enabled.aea7a

23、ea6/pci660pci frequency selection (pci66)0 - pci operates at 33 mhz (default).1 - pci operates at 66 mhz.if the pci peripheral is disabled (pci_en = 0), this pin must not bepulled up.aea5/mcbsp1_en0mcbsp1 enable bit (mcbsp1_en)0 - gpio pin functions enabled (default).1 - mcbsp1 pin functions enabled.aseyas4c/lkout_en0sysclkout enable pin (sysclkout_en)0 - gp1 pin function of the sysclk4/gp1 pin enabled (default).1 - sysclk4 pin function of the sysclk4/gp1 pin enabled.aea31srio使能： 上拉srio不使能：下拉aea2