基于VHDL_的_数字钟的设计.doc

顶层文件- company: - engineer: - - create date: 09:40:47 01/14/2014 - design name: - module name: digital_clock - behavioral - project name: - target devices: - tool versions: - description: - dependencies: - revision: - revision 0.01 - file created- additional comments: -library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following library declaration if using- arithmetic functions with signed or unsigned values-use ieee.numeric_std.all;- uncomment the following library declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity digital_clock is port(setup : in std_logic;-预置脉冲手动set : in std_logic;-upd0选择工作模式clk : in std_logic;-输入1khz脉冲 需要经过1000分频 产生1hz脉冲tn : in std_logic;-相当于题目要求中的up 为高时 预置+1 为低时-1en : in std_logic;-使能h_year : out std_logic_vector(3 downto 0);h_year1 : out std_logic_vector(3 downto 0);m_mon : out std_logic_vector(3 downto 0);m_mon1 : out std_logic_vector(3 downto 0);s_day : out std_logic_vector(3 downto 0);s_day1 : out std_logic_vector(3 downto 0);end digital_clock;architecture bdf_type of digital_clock is component daymony1port(clk0 : in std_logic; en : in std_logic; lock : in std_logic_vector(2 downto 0); da0 : out std_logic_vector(3 downto 0); da1 : out std_logic_vector(3 downto 0); mo0 : out std_logic_vector(3 downto 0); mo1 : out std_logic_vector(3 downto 0); ya0 : out std_logic_vector(3 downto 0); ya1 : out std_logic_vector(3 downto 0);end component;component fenpinport(upd0 : in std_logic;-外接顶层set clk : in std_logic;-外接顶层f10 f_clk : out std_logic;-分频输出为1hz lock : out std_logic_vector(2 downto 0)-计数set脉冲 000-111循环产生工作模式);end component;component s_m_hourport(clk0 : in std_logic; en : in std_logic; lock : in std_logic_vector(2 downto 0); co : out std_logic; h0 : out std_logic_vector(3 downto 0); h1 : out std_logic_vector(3 downto 0); m0 : out std_logic_vector(3 downto 0); m1 : out std_logic_vector(3 downto 0); s0 : out std_logic_vector(3 downto 0); s1 : out std_logic_vector(3 downto 0);end component;component yuzhisport(clk1 : in std_logic; tn : in std_logic; en : in std_logic; lock : in std_logic_vector(2 downto 0); da0 : out std_logic_vector(3 downto 0); da1 : out std_logic_vector(3 downto 0); mo0 : out std_logic_vector(3 downto 0); mo1 : out std_logic_vector(3 downto 0); ya0 : out std_logic_vector(3 downto 0); ya1 : out std_logic_vector(3 downto 0);end component;component s_m_yuz1port(clk1 : in std_logic; tn : in std_logic; en : in std_logic; lock : in std_logic_vector(2 downto 0); h0 : out std_logic_vector(3 downto 0); h1 : out std_logic_vector(3 downto 0); m0 : out std_logic_vector(3 downto 0); m1 : out std_logic_vector(3 downto 0); s0 : out std_logic_vector(3 downto 0); s1 : out std_logic_vector(3 downto 0);end component;component xuanze1 port( en : in std_logic; lock : in std_logic_vector(2 downto 0); -工作模式选择 a0 : in std_logic_vector(3 downto 0); a1 : in std_logic_vector(3 downto 0);-s b0 : in std_logic_vector(3 downto 0); b1 : in std_logic_vector(3 downto 0);-mc0 : in std_logic_vector(3 downto 0); c1 : in std_logic_vector(3 downto 0);-h d0 : in std_logic_vector(3 downto 0); d1 : in std_logic_vector(3 downto 0);-se0 : in std_logic_vector(3 downto 0); e1 : in std_logic_vector(3 downto 0);-m f0 : in std_logic_vector(3 downto 0); f1 : in std_logic_vector(3 downto 0);-h s0,s1 : out std_logic_vector(3 downto 0); m0,m1 : out std_logic_vector(3 downto 0); h0,h1 : out std_logic_vector(3 downto 0) );end component;component xuanze2 port( en : in std_logic; lock : in std_logic_vector(2 downto 0); -工作模式选择 a0 : in std_logic_vector(3 downto 0); a1 : in std_logic_vector(3 downto 0);-日 b0 : in std_logic_vector(3 downto 0); b1 : in std_logic_vector(3 downto 0);-月c0 : in std_logic_vector(3 downto 0); c1 : in std_logic_vector(3 downto 0);-年 d0 : in std_logic_vector(3 downto 0); d1 : in std_logic_vector(3 downto 0);-日e0 : in std_logic_vector(3 downto 0); e1 : in std_logic_vector(3 downto 0);-月 f0 : in std_logic_vector(3 downto 0); f1 : in std_logic_vector(3 downto 0);-年 da0,da1 : out std_logic_vector(3 downto 0); mo0,mo1 : out std_logic_vector(3 downto 0); ya0,ya1 : out std_logic_vector(3 downto 0) );end component;component time_showport( en : in std_logic; lock : in std_logic_vector(2 downto 0);-显示切换义马管具体显示就不写了只解决显示切换模块 s_s0 : in std_logic_vector(3 downto 0); s_s1 : in std_logic_vector(3 downto 0); s_m0 : in std_logic_vector(3 downto 0); s_m1 : in std_logic_vector(3 downto 0); s_h0 : in std_logic_vector(3 downto 0); s_h1 : in std_logic_vector(3 downto 0); s_da0 : in std_logic_vector(3 downto 0); s_da1 : in std_logic_vector(3 downto 0); s_mo0 : in std_logic_vector(3 downto 0); s_mo1 : in std_logic_vector(3 downto 0); s_ya0 : in std_logic_vector(3 downto 0); s_ya1 : in std_logic_vector(3 downto 0); ah_year : out std_logic_vector(3 downto 0);ah_year1 : out std_logic_vector(3 downto 0);am_mon : out std_logic_vector(3 downto 0);am_mon1 : out std_logic_vector(3 downto 0);as_day : out std_logic_vector(3 downto 0);as_day1 : out std_logic_vector(3 downto 0);end component;signalsynthesized_wire_8 : std_logic;-连接工作时钟signalsynthesized_wire_1 : std_logic;-连接时分秒的进位输出signalsynthesized_wire_9 : std_logic_vector(2 downto 0);-连接locksignal s0a0: std_logic_vector(3 downto 0);signal s1a1: std_logic_vector(3 downto 0);signal m0b0: std_logic_vector(3 downto 0);signal m1b1: std_logic_vector(3 downto 0);signal h0c0: std_logic_vector(3 downto 0);signal h1c1: std_logic_vector(3 downto 0);signal s0d0: std_logic_vector(3 downto 0);signal s1d1: std_logic_vector(3 downto 0);signal m0e0: std_logic_vector(3 downto 0);signal m1e1: std_logic_vector(3 downto 0);signal h0f0: std_logic_vector(3 downto 0);signal h1f1: std_logic_vector(3 downto 0);signal da0a0: std_logic_vector(3 downto 0);signal da1a1: std_logic_vector(3 downto 0);signal mo0b0: std_logic_vector(3 downto 0);signal mo1b1: std_logic_vector(3 downto 0);signal ya0c0: std_logic_vector(3 downto 0);signal ya1c1: std_logic_vector(3 downto 0);signal da0d0: std_logic_vector(3 downto 0);signal da1d1: std_logic_vector(3 downto 0);signal mo0e0: std_logic_vector(3 downto 0);signal mo1e1: std_logic_vector(3 downto 0);signal ya0f0: std_logic_vector(3 downto 0);signal ya1f1: std_logic_vector(3 downto 0);signal m1: std_logic_vector(3 downto 0);signal m2: std_logic_vector(3 downto 0);signal m3: std_logic_vector(3 downto 0);signal m4: std_logic_vector(3 downto 0);signal m5: std_logic_vector(3 downto 0);signal m6: std_logic_vector(3 downto 0);signal m7: std_logic_vector(3 downto 0);signal m8: std_logic_vector(3 downto 0);signal m9: std_logic_vector(3 downto 0);signal m10: std_logic_vector(3 downto 0);signal m11: std_logic_vector(3 downto 0);signal m12: std_logic_vector(3 downto 0);begin u1 : daymony1port map(clk0 = synthesized_wire_8, en = synthesized_wire_1, lock = synthesized_wire_9, da0 = da0a0, da1 = da1a1, mo0 = mo0b0, mo1 = mo1b1, ya0 = ya0c0, ya1 = ya1c1);-u2 : fenpinport map(upd0 =set, clk = clk, f_clk= synthesized_wire_8, lock = synthesized_wire_9);-u3 : s_m_hourport map(clk0 = synthesized_wire_8, en = en, lock = synthesized_wire_9, co = synthesized_wire_1, h0 = h0c0, h1 = h1c1, m0 = m0b0, m1 = m1b1, s0 = s0a0, s1 = s1a1);u4: yuzhisport map(clk1 = setup, tn = tn, en = en, lock = synthesized_wire_9, da0 = da0d0, da1 = da1d1, mo0 = mo0e0, mo1 = mo1e1, ya0 = ya0f0, ya1 = ya1f1);u5 : s_m_yuz1port map( clk1 = setup, tn = tn, en = en, lock = synthesized_wire_9, h0 = h0f0, h1 = h1f1, m0 = m0e0, m1 = m1e1, s0 = s0d0, s1 = s1d1);u6 : xuanze1port map ( en = en, lock = synthesized_wire_9, a0 = s0a0, a1 = s1a1, b0 = m0b0, b1 = m1b1,c0 = h0c0, c1 = h1c1, d0 = s0d0, d1 = s1d1,e0 = m0e0, e1 = m1e1, f0 = h0f0, f1 = h1f1, s0 = m1,s1 = m2, m0 = m3,m1 = m4, h0 = m5,h1 = m6 );u7 : xuanze2port map ( en = en, lock = synthesized_wire_9,-没完成 a0 = da0a0, a1 = da1a1, b0 = mo0b0, b1 = mo1b1,c0 = ya0c0, c1 = ya1c1, d0 = da0d0, d1 = da1d1,e0 = mo0e0, e1 = mo1e1, f0 = ya0f0, f1 = ya1f1, da0 = m7, da1 = m8, mo0 = m9, mo1 = m10, ya0 = m11, ya1 = m12 );u8 : time_showport map ( en = en, lock = synthesized_wire_9,-显示切换义马管具体显示就不写了只解决显示切换模块 s_s0 = m1, s_s1 = m2, s_m0 =m3, s_m1 = m4, s_h0 = m5, s_h1 = m6, s_da0 = m7, s_da1 = m8, s_mo0 = m9, s_mo1 = m10, s_ya0 = m11, s_ya1 = m12,ah_year = h_year , ah_year1 = h_year1,am_mon = m_mon,am_mon1 = m_mon1,as_day = s_day,as_day1 = s_day1 );end bdf_type;daymony1年月日library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following lines to use the declarations that are- provided for instantiating xilinx primitive components.-library unisim;-use unisim.vcomponents.all;entity daymony1 is port( clk0 : in std_logic; da0,da1 : out std_logic_vector(3 downto 0); mo0,mo1 : out std_logic_vector(3 downto 0); ya0,ya1 : out std_logic_vector(3 downto 0); en : in std_logic;-en接上一个模块小时的进位 lock : in std_logic_vector(2 downto 0) ); end daymony1;architecture behavioral of daymony1 is signal dat0 : std_logic_vector(3 downto 0):=0110;signal dat1 : std_logic_vector(3 downto 0):=0001;signal mon0 : std_logic_vector(3 downto 0):=0001;signal mon1 : std_logic_vector(3 downto 0):=0000;signal yea0 : std_logic_vector(3 downto 0):=0100;signal yea1 : std_logic_vector(3 downto 0):=0001;signal day_out,month_out:std_logic;-程序内部天和月的进位，也可放于前面设为bufferbeginda0=dat0;da1=dat1;mo0=mon0;mo1=mon1;ya0=yea0;ya1=yea1;-年月日赋初值p1:process (clk0,en,lock)-天的输出，分大月和小月，以及二月beginif en=1then -时分秒模块有进位使能年月日 if lock=001then if clk0event and clk0=1then if (mon0=0001and mon1=0000)or(mon0=0011and mon1=0000) or(mon0=0101and mon1=0000)or(mon0=0111and mon1=0000) or(mon0=1000and mon1=0000)or(mon0=0000and mon1=0001) or(mon0=0010and mon1=0001)then -1 3 5 7 8 10 12月为31天 if dat0=0001 and dat1=0011then dat0=0001;dat1=0000;day_out=1; elsif dat0=1001then dat0=0000;dat1=dat1+1;day_out=0; else dat0=dat0+1;dat1=dat1;day_out=0; end if; elsif(mon0=0100and mon1=0000)or(mon0=0110and mon1=0000) or(mon0=1001and mon1=0000)or(mon0=0001and mon1=0001)then -4 6 9 11月份30天 if dat0=0000 and dat1=0011then dat0=0001;dat1=0000;day_out=1; elsif dat0=1001then dat0=0000;dat1=dat1+1;day_out=0; else dat0=dat0+1;dat1=dat1;day_out=0; end if; else -对闰年的判断2月29数码管只显示年后两位 前两位默认为20 故只要后两位能被4整除即使闰年 if(yea1=0000or yea1=0010or yea1=0100or yea1=0110 or yea1=01000)and(yea0=0000 or yea0=0100or yea0=01000)or (yea1=0001 or yea1=0011 or yea1=0101or yea1=0111 or yea1=1001)and(yea0=0010or yea0=0110) then if dat0=1001 and dat1=0010then dat0=0001;dat1=0000;day_out=1; elsif dat0=1001then dat0=0000;dat1=dat1+1;day_out=0; else dat0=dat0+1;dat1=dat1;day_out=0; end if; else-不是闰年，二月份28天 if dat0=1000 and dat1=0010then dat0=0001;dat1=0000;day_out=1; elsif dat0=1001then dat0=0000;dat1=dat1+1;day_out=0; else dat0=dat0+1;dat1=dat1;day_out=0; end if; end if;-判断闰年的语句 end if;-判断月份的语句 end if;-对应clk0 end if;-对应lock end if;-对应使能end process p1;p2:process (day_out,lock)-对月的输出begin if lock=001then if day_outevent and day_out=1then -天数产生进位使月份加一 if mon0=0010 and mon1=0001then mon0=0001;mon1=0000;month_out=1;-到十二月份后重新回到一月份产生月进位给年 elsif mon0=1001then mon0=0000;mon1=mon1+1;month_out=0; else mon0=mon0+1;mon1=mon1;month_out=0; end if; end if; end if;end process p2;p3:process (month_out,lock)-对年的设制begin if lock=001then if month_outevent and month_out=1then -月份产生进位使年加一 if yea0=1001and yea1=1001then yea0=0000;yea1=0000; elsif yea0=1001then yea0=0000;yea1=yea1+1; else yea0=yea0+1;yea1=yea1; end if; end if; end if;end process p3;end behavioral;分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following lines to use the declarations that are- provided for instantiating xilinx primitive components.-library unisim;-use unisim.vcomponents.all;entity fenpin is port(upd0 : in std_logic; clk : in std_logic; f_clk : out std_logic; lock : out std_logic_vector(2 downto 0) );end fenpin;architecture behavioral of fenpin issignal tem : std_logic_vector(2 downto 0):=000;signal cout : std_logic_vector(8 downto 0):=000000000;signal clk_o :std_logic;begin lock=tem;f_clk=clk_o; process(upd0,clk ,cout) beginif clk event and clk =1then if cout=111110011then cout=000000000; clk_o=not clk_o; else cout=cout+1; end if;end if;if upd0event and upd0=1then tem=tem+1;end if; end process;end behavioral;时分秒library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following lines to use the declarations that are- provided for instantiating xilinx primitive components.-library unisim;-use unisim.vcomponents.all;entity s_m_hour is port( clk0: in std_logic; -clk0工作时钟，clk1预置脉冲 lock : in std_logic_vector(2 downto 0); -工作模式选择 s0,s1 : out std_logic_vector(3 downto 0); m0,m1 : out std_logic_vector(3 downto 0); h0,h1 : out std_logic_vector(3 downto 0); co : out std_logic;-_vector(2 downto 0); -hour产生进位 en : in std_logic );end s_m_hour;architecture behavioral of s_m_hour issignal ts0 : std_logic_vector(3 downto 0):=0100;signal ts1 : std_logic_vector(3 downto 0):=0101;signal tm0 : std_logic_vector(3 downto 0):=1001;signal tm1 : std_logic_vector(3 downto 0):=0101;signal th0 : std_logic_vector(3 downto 0):=0011;signal th1 : std_logic_vector(3 downto 0):=0010;signal cc : std_logic;begins0=ts0;s1=ts1;m0=tm0;m1=tm1;h0=th0;h1=th1;co=cc; p2: process(c